SI5318-G-BC Silicon Laboratories Inc, SI5318-G-BC Datasheet - Page 17

• Manufacturer Part Number: SI5318-G-BC
• Description: IC MULTIPLIER SONET/SDH 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5318-G-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 173MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 173MHz
• Operating Supply Voltage: 3.3 V
• Supply Current: 140 mA
• Operating Temperature Range: - 55 C to + 150 C
• Mounting Style: SMD/SMT
• Operating Frequency: 622 MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1183

The Si5318 also provides an output indicating the digital
hold status of the device, DH_ACTV. The Si5318 only
enters the digital hold mode upon the loss of the input
clock. When this occurs, the LOS alarm will also be
active. Therefore, applications that require monitoring of
the status of the Si5318 need only monitor the
CAL_ACTV and either the LOS or DH_ACTV outputs to
know the state of the device.
2.7. Reset
The Si5318 provides a Reset/Calibration pin, RSTN/
CAL, which resets the device and disables the outputs.
When the RSTN/CAL pin is driven low, the internal
circuitry enters into the reset mode, and all LVTTL
outputs are forced into a high-impedance state. Also,
the CLKOUT+ and CLKOUT– pins are forced to a
nominal CML logic LOW and HIGH respectively (See
Figure 9). This feature is useful in in-circuit test
applications. A low-to-high transition on RSTN/CAL
initializes all digital logic to a known condition and
initiates self-calibration of the DSPLL. Upon completion
of self-calibration, the DSPLL begins to lock to the clock
input signal.
2.8. PLL Self-Calibration
The Si5318 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss of power condition. Self-
calibration can also be manually initiated by a low-to-
high transition on the RSTN/CAL input.
Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires the
presence of a valid input clock.
Figure 9. CLKOUT± Equivalent Circuit, RSTN/
100 Ω
15 mA
V
CAL asserted LOW
DD
2.5 V
100 Ω
CLKOUT–
CLKOUT+
Rev. 1.0
If the self-calibration is initiated without a valid clock
present, the device waits for a valid clock before
completing the self-calibration. The Si5318 clock output
is set to the lower end of the operating frequency range
while the device is waiting for a valid clock. After the
clock input is validated, the calibration process runs to
completion; the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost following self-
calibration, the device enters digital hold mode. When
the input clock returns, the device re-locks to the input
clock without performing a self-calibration. During the
calibration process, the output clock frequency is
indeterminate and may jump as high as 5% above the
final locked value.
2.9. Bias Generation Circuitry
The Si5318 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 k Ω
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5318 provides a differential input for the clock
input, CLKIN. This input is internally biased to a voltage
of V
differential or single-ended driver circuit. For differential
transmission lines, the termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
The Si5318 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation, simply connect to
either CLKOUT+ or CLKOUT–, and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5318 incorporates an on-chip voltage regulator.
The
compensation circuit of one resistor and one capacitor
to ensure stability over all operating conditions.
Internally, the Si5318 V
on-chip voltage regulator input, and the V
supply power to the device’s LVTTL I/O circuitry. The
V
and are also used for connection of the external
compensation circuit.
DD25
ICM
pins supply power to the core DSPLL circuitry
voltage
(see Table 2 on page 6) and may be driven by a
regulator
DD33
pins are connected to the
requires
Si5318
DD33
an
pins also
external
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