EL4585CS-T13 Intersil, EL4585CS-T13 Datasheet - Page 7
![IC GENLOCK HORZ 8FSC 16-SOIC](/photos/5/65/56533/20-16-soic_sml.jpg)
EL4585CS-T13
Manufacturer Part Number
EL4585CS-T13
Description
IC GENLOCK HORZ 8FSC 16-SOIC
Manufacturer
Intersil
Type
Phase Lock Loop (PLL)r
Datasheet
1.EL4585CSZ.pdf
(15 pages)
Specifications of EL4585CS-T13
Pll
Yes
Input
Clock
Output
CMOS, TTL
Number Of Circuits
1
Ratio - Input:output
3:1
Differential - Input:output
No/No
Frequency - Max
36MHz
Divider/multiplier
Yes/No
Voltage - Supply
5V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
36MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Typical Performance Curves
EL4585 Block Diagram
Description Of Operation
The horizontal sync signal (CMOS level, falling leading edge)
is input to H
200ns, the falling edge of which becomes the reference to
which the clock output will be locked (See “Timing Diagrams”
on page 5). The clock is generated by the signal on pin 5,
OSC IN. There are 2 general types of VCO that can be used
with the EL4585, LC and crystal controlled. Additionally,
each type can be either built up using discrete components,
including a varactor as the frequency controlling element, or
complete, self contained modules can be purchased with
everything inside a metal can. These modules are very
forgiving of PCB layout, but cost more than discrete
solutions. The VCO or VCXO is used to regulate the clock.
An LC tank resonator has greater “pull” than a crystal
controlled circuit, but will also be more likely to drift over
time, and thus will generate more jitter. The “pullability” of the
circuit refers to the ability to pull the frequency of oscillation
away from its center frequency by modulating the voltage on
the control pin of the VCO module or varactor, and is a
function of the slope and range of the capacitance-voltage
curve of the varactor or VCO module used. The VCO signal
FIGURE 6. POWER DISSIPATION vs AMBIENT
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
SYNC
0
0
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.23W
0.91W
θ
input (pin 10). This signal is delayed about
SO16 (0.150”)
JA
25
= +110°C/W
AMBIENT TEMPERATURE (°C)
50
θ
JA
PDIP16
7
= +81°C/W
75
85
100
(Continued)
125
150
EL4585
is sent to the CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined by the state
of pins 1, 2, and 16 and is described in Table 1. The divided
signal is sent, along with the delayed H
phase/frequency detector, which compares the two signals
for phase and frequency differences. Any phase difference is
converted to a current at the charge pump output, (pin 7). A
VCO with a positive frequency deviation with control voltage
must be used. Varactors have negative capacitance slope
with voltage, resulting in positive frequency deviation with
increasing control voltage for the oscillators in Figures 10
and 11.
VCO
The VCO should be tuned so that its frequency of oscillation
is very close to the required clock output frequency when the
voltage on the varactor is 2.5V. VCXO and VCO modules are
already tuned to the desired frequency, so this step is not
necessary if using one of these units. The output range of
the charge pump output (pin 7) is 0V to 5V, and it can source
or sink a maximum of about 300µA, so all frequency control
must be accomplished with variable capacitance from the
FIGURE 7. POWER DISSIPATION vs AMBIENT
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TEMPERATURE
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.43W
1.25W
θ
SO16 (0.150”)
JA
25
= +80°C/W
AMBIENT TEMPERATURE (°C)
50
θ
JA
PDIP16
= +70°C/W
75
100
SYNC
125
input, to the
September 3, 2009
150
FN7175.4