SI4133T-BM Silicon Laboratories Inc, SI4133T-BM Datasheet - Page 20

• Manufacturer Part Number: SI4133T-BM
• Description: IC RF SYNTHESIZER DUAL 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133T-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Aero
4.1. Receive Section
The Aero transceiver uses a low-IF receiver architecture
that allows for the on-chip integration of the channel
selection filters, eliminating the external RF image reject
filters and the IF SAW filter required in conventional
superheterodyne architectures. Compared to a direct-
conversion architecture, the low-IF architecture has a
much greater degree of immunity to dc offsets that can
arise from RF local oscillator (RFLO) self-mixing, 2nd-
order distortion of blockers, and device 1/f noise. This
relaxes the common-mode balance requirements on the
input SAW filters and simplifies PC board design and
manufacturing.
The Si4200 integrates three differential-input LNAs. The
GSM input supports the GSM 850 (869–894 MHz) or E-
GSM 900 (925–960 MHz) bands. The DCS input
supports the DCS 1800 (1805–1880 MHz) band. The
PCS input supports the PCS 1900 (1930–1990 MHz)
band. For quad-band designs, SAW filters for the
GSM 850 and E-GSM 900 bands should be connected
to a balanced combiner that drives the GSM input for
both
Si4200DB-BM, the PCS input should be used for either
DCS 1800 or PCS 1900 bands.
The LNA inputs are matched to the 150 or 200 Ω
balanced-output SAW filters through external LC
matching networks. See “AN49: Aero Transceiver PCB
Layout Guidelines” for implementation details. The LNA
gain is controlled with the LNAG[1:0] and LNAC[1:0] bits
in register 05h.
A quadrature image-reject mixer downconverts the RF
signal to a 100 kHz intermediate frequency (IF) with the
RFLO from the Si4133T frequency synthesizer. The
RFLO frequency is between 1737.8 and 1989.9 MHz,
and is divided by two in the Si4200 for GSM 850 and E-
20
bands.
GSM
DCS
PCS
For
dual-band
RXBAND[1:0]
LNAC[1:0]
LNAG[1:0]
LNA
LNA
LNA
designs
Figure 13. Receiver Block Diagram
0 / 90
PLL
RF
using
AGAIN[2:0]
PGA
PGA
N
RFUP
RF1
Si4133T
[15:0]
the
Rev. 1.4
Si4200
ADC
ADC
GSM 900 modes. The mixer output is amplified with an
analog programmable gain amplifier (PGA), which is
controlled with the AGAIN[2:0] bits in register 05h. The
quadrature IF signal is digitized with high resolution A/D
converters (ADCs).
The Si4201 downconverts the ADC output to baseband
with a digital 100 kHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to
remove blocking and reference interference signals.
The response of the IIR filter is programmable to a high
selectivity setting (CSEL = 0) or a low selectivity setting
(CSEL = 1). The low selectivity filter has a flatter group
delay response that may be desirable where the final
channelization filter is in the baseband chip. After
channel selection, the digital output is scaled with a
digital PGA, which is controlled with the DGAIN[5:0] bits
in register 05h.
The LNAG[1:0], LNAC[1:0], AGAIN[2:0] and DGAIN[5:0]
bits must be set to provide a constant amplitude signal
to the baseband receive inputs. See “AN51: Aero
Transceiver AGC Strategy” for more details.
DACs drive a differential analog signal onto the RXIP,
RXIN, RXQP and RXQN pins to interface to standard
analog-input baseband ICs. No special processing is
required in the baseband for offset compensation or
extended dynamic range. The receive and transmit
baseband I/Q pins can be multiplexed together into a 4-
wire interface. The common mode level at the receive I
and Q outputs is programmable with the DACCM[1:0]
bits, and the full scale level is programmable with the
DACFS[1:0] bits in register 12h.
100 kHz
CSEL
DGAIN[5:0]
PGA
PGA
ZERODEL[2:0]
DACCM[1:0]
DACFS[1:0]
Si4201
DAC
DAC
Q
I