MC100LVEL39DW ON Semiconductor, MC100LVEL39DW Datasheet

MC100LVEL39DW

Manufacturer Part Number

MC100LVEL39DW

Description

IC CLOCK GEN ECL 2/4 4/6 20SOIC

Manufacturer

ON Semiconductor

Series

100LVELr

Type

Clock Generatorr

Datasheet

1.MC100LVEL39DWR2G.pdf (6 pages)

Specifications of MC100LVEL39DW

Pll

Input

LVDS, NECL, PECL

Output

ECL

Number Of Circuits

Ratio - Input:output

1:4

Differential - Input:output

Yes/Yes

Frequency - Max

1GHz

Divider/multiplier

Yes/No

Voltage - Supply

±3 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Frequency-max

1GHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

MC100LVEL39DWOS

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MC100LVEL39DW

Manufacturer:

ON/安森美

Quantity:

20 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

MC100LVEL39DWR2

Manufacturer:

Quantity:

20 000

Current page: 1 of 6
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MC100LVEL39

3.3V ECL ÷2/4, ÷4/6 Clock

Generation Chip

Description

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by

either a differential or single-ended input signal. In addition, by using

the V

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen with

an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip−flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

therefore, for systems which utilize multiple LVEL39s, the Master Reset

(MR) input must be asserted to ensure synchronization. For systems

which only use one LVEL39, the MR pin need not be exercised as the

internal divider design ensures synchronization between the ÷2/4 and the

÷4/6 outputs of a single device.

device only. For single-ended input conditions, the unused differential

input is connected to V

rebias AC coupled inputs. When used, decouple V

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2008 − Rev. 10

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip

The common enable (EN) is synchronous so that the internal dividers

Upon startup, the internal flip-flops will attain a random state;

The V

ESD Protection: Human Body Model; >2 kV

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range:

NECL Mode Operating Range:

Internal Input Pulldown Resistors

Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

50 ps Maximum Output-to-Output Skew

Synchronous Enable/Disable

Master Reset for Synchronization

= 3.0 V to 3.8 V with V

= 0 V with V

output, a sinusoidal source can be AC coupled into the device.

pin, an internally generated voltage supply, is available to this

should be left open.

= −3.0 V to −3.8 V

as a switching reference voltage. V

= 0 V

and V

may also

via a

•

Moisture Sensitivity Pb = Level 1

For Additional Information, see Application Note

AND8003/D

Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

Transistor Count = 419 devices

Pb−Free Packages are Available*

*For additional marking information, refer to

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Application Note AND8002/D.

ORDERING INFORMATION

MARKING DIAGRAM*

Pb−Free = Level 3

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

AWLYYWWG

DW SUFFIX

CASE 751D

SO−20 WB

100LVEL39

Publication Order Number:

MC100LVEL39/D

Related parts for MC100LVEL39DW

MC100LVEL39DW Summary of contents

Page 1

... Internal Input Pulldown Resistors • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 10 MARKING DIAGRAM* ...

Page 2

DIVSELb CLK CLK Warning: All V and V pins must be externally ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 5. LVNECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 5

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEL39DW MC100LVEL39DWG MC100LVEL39DWR2 MC100LVEL39DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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