MC14536BDWG ON Semiconductor, MC14536BDWG Datasheet - Page 10
![IC TIMER PROGR 24STAGE 16-SOIC](/photos/5/67/56711/488-16-soic_sml.jpg)
MC14536BDWG
Manufacturer Part Number
MC14536BDWG
Description
IC TIMER PROGR 24STAGE 16-SOIC
Manufacturer
ON Semiconductor
Type
Programmable Timerr
Specifications of MC14536BDWG
Frequency
2MHz
Voltage - Supply
3 V ~ 18 V
Current - Supply
15µA
Operating Temperature
-55°C ~ 125°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Number Of Internal Timers
1
Supply Voltage (max)
18 V
Supply Voltage (min)
3 V
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Propagation Delay (max)
3600 ns @ 5 V or 1300 ns @ 10 V or 1000 ns @ 15 V
Circuit Type
Low-Power Schottky
Current, Supply
600 μA
Function Type
24-Stages
Logic Function
Programmable
Logic Type
CMOS
Package Type
SOIC-16
Special Features
Binary
Temperature, Operating, Range
-55 to +125 °C
Voltage, Supply
3 to 18 VDC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC14536BDWG
MC14536BDWGOS
MC14536BDWGOS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC14536BDWG
Manufacturer:
ON
Quantity:
2 416
NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET
DECODE OUT
input low enables the chip’s internal counters. After RESET goes low, the 2
DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2
intervals where n = the number of stages selected from the truth table.
RESET
CLOCK
PULSE
GEN.
IN
POWERUP
1
Figure 12. Time Interval Configuration Using an External Clock, Reset, and
*t
C
R
w
X
X
Output Monostable to Achieve a Pulse Output
(Divide−by−4 Configured)
10
12
15
14
11
6
9
2
1
7
3
http://onsemi.com
8−BYPASS
A
B
C
D
RESET
SET
CLOCK INH
MONO−IN
OSC INH
IN
1
MC14536B
10
V
V
+V
DD
SS
16
8
DECODE OUT
OUT 1
OUT 2
n
/2 negative transition of the clock input causes
13
4
5
*t
t
R
C
w
w
X
X
in msec
≈ .00247 • R
in kW
in pF
n
x (the clock period)
X
• C
X
0.85