DS1672U-33+ Maxim Integrated Products, DS1672U-33+ Datasheet - Page 5

• Manufacturer Part Number: DS1672U-33+
• Description: IC TIMEKEEPER 3.3V 32-BIT 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1672U-33+

• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Function: Clock/Calendar/Elapsed Time Counter
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS
(V
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
Note 8:The maximum t
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
Note 10: C
SCL Clock
Frequency
Bus Free Time
Between a STOP and
START Condition
Hold Time
(Repeated) START
Condition
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both
SDA and SCL
Signals
Fall Time of Both
SDA and SCL
Signals
Setup Time for STOP
Condition
Capacitive Load for
Each Bus Line
I/O Capacitance
CC
PARAMETER
= 0V, T
order to bridge the undefined region of the falling edge of SCL.
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
line is released.
B
–Total capacitance of one bus line in pF.
A
= -40C to +85C.)
HD:DAT
has only to be met if the device does not stretch the LOW period (t
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
f
t
C
HIGH
LOW
C
BUF
SCL
t
t
R
I/O
F
B
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
CONDITIONS
5 of 15
20 + 0.1C
20 + 0.1C
MIN
100
100
250
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.0
0
0
R
B
B
max + t
TYP
10
SU:DAT
SU:DAT
LOW
≥ to 250ns must then be met. This will
) of the SCL signal.
= 1000 + 250 = 1250ns before the SCL
MAX
1000
400
100
300
300
300
400
0.9
IHMIN
UNITS
kHz
pF
pF
s
s
s
s
s
s
s
ns
ns
ns
of the SCL signal) in
NOTES
7, 8
10
10
10
6
9