M48T37V-10MH1F STMicroelectronics, M48T37V-10MH1F Datasheet - Page 17

• Manufacturer Part Number: M48T37V-10MH1F
• Description: IC TIMEKPR NVRAM 256KB 3V 44-SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37V-10MH1F

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4718-2

M48T37Y, M48T37V
3.7
3.8
The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the
watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to
the watchdog register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied. The WDI pin should be connected to V
Power-on reset
The M48T37Y/V continuously monitors V
point, the RST pulls low (open drain) and remains low on power-up for t
passes V
an appropriate resistor to V
page
Programmable interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an
interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the flag register
7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the watchdog steering
(WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.
The alarm flag and the IRQ/FT output are cleared by a READ to the flags register. An
interrupt condition reset will not occur unless the addresses are stable at the flag location for
at least 15 ns while the device is in the READ mode as shown in
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 kΩ
recommended) to V
occurs or the frequency test mode is enabled.
22).
PFD
. RST is valid for all V
CC
. The pin remains in the high impedance state unless an interrupt
CC
should be chosen to control rise time (see
Doc ID 7019 Rev 9
CC
conditions. The RST pin is an open drain output and
CC
. When V
CC
falls to the power fail detect trip
Figure 7 on page
REC
SS
Clock operations
Figure 13 on
if not used.
after V
CC
14.
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