m48t37v STMicroelectronics, m48t37v Datasheet

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m48t37v

Manufacturer Part Number
m48t37v
Description
5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
Manufacturer
STMicroelectronics
Datasheet

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Features
August 2007
(V
Integrated ultra-low power SRAM, real time
clock, power-fail control circuit, and battery
Frequency test output for real time clock
software calibration
Year 2000 compliant
Automatic power-fail chip deselect and WRITE
protection
Watchdog timer
WRITE protect voltage
– M48T37Y:V
– M48T37V: V
Packaging includes a 44-lead SOIC and
SNAPHAT
SOIC package provides direct connection for a
SNAPHAT
crystal
Microprocessor power-on reset (valid even
during battery back-up mode)
Programmable alarm output active in the
battery back-up mode
Battery low flag
RoHS compliant
– Lead-free second level interconnect
PFD
4.2V
2.7V
= Power-Fail Deselect Voltage):
V
V
®
®
PFD
PFD
top which contains the battery and
top (to be ordered separately)
5.0 or 3.3V, 256 Kbit (32 Kbit x 8) TIMEKEEPER
CC
CC
= 4.5 to 5.5V
4.5V
3.0V
= 3.0 to 3.6V
Rev 7
44
SNAPHAT (SH)
Battery/Crystal
SOH44 (MH)
44-pin SOIC
1
M48T37Y
M48T37V
®
SRAM
www.st.com
1/29
1

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m48t37v Summary of contents

Page 1

... Watchdog timer ■ WRITE protect voltage (V = Power-Fail Deselect Voltage): PFD – M48T37Y:V = 4.5 to 5.5V CC 4.2V V 4.5V PFD – M48T37V 3.0 to 3.6V CC 2.7V V 3.0V PFD ■ Packaging includes a 44-lead SOIC and ® SNAPHAT top (to be ordered separately) ■ SOIC package provides direct connection for a ® ...

Page 2

Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Figure 1. Logic diagram ® RAM non-volatile static RAM and real time ® battery/crystal package to be mounted on top of Table 18 on page A0-A14 W M48T37Y M48T37V E G WDI V SS 27). DQ0-DQ7 RST IRQ/FT AI02172 5/29 ...

Page 6

... Not connected Internally RST A14 5 40 A12 M48T37Y NC 12 M48T37V WDI DQ0 18 27 DQ1 19 26 DQ2 AI02174 ...

Page 7

Figure 3. Block diagram IRQ/FT OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL LITHIUM CELL VOLTAGE SENSE SWITCHING V CC WDI POWER V PFD AND CIRCUITRY RST BiPORT SRAM ARRAY A0-A14 32,752 x 8 DQ0-DQ7 SRAM ARRAY E ...

Page 8

Operation modes As Figure 3 on page 7 oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that provide user accessible BYTEWIDE™ clock information are in the bytes with addresses 7FF1 and 7FF9h-7FFFh (located in ...

Page 9

... Address Access. AXQX tAVAV VALID tAVQV tELQV tELQX tGLQV tGLQX (1) Parameter = 0 to 70°C or –40 to 85° GLQV AVQV tAXQX tEHQZ tGHQZ VALID AI00925 M48T37Y M48T37V –70 –100 Min Max Min Max 70 100 70 100 70 100 ...

Page 10

Write mode The M48T37Y the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge WRITE is terminated by the earlier ...

Page 11

... A CC falls within the V (max PFD . Therefore, decoupling of the power CC drops below less than system power returns and after V reaches V REC CC M48T37V –100 Unit Max Min Max 100 ...

Page 12

Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be ...

Page 13

Table 5. Register map Address 7FFFh 10 Years 7FFEh 7FFDh Date 7FFCh 7FFBh Hours 7FFAh 0 10 Minutes 7FF9h ST 10 Seconds 7FF8h W R ...

Page 14

Setting the alarm clock Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a predetermined time on a specific day of the month or repeat every day, hour, minute, or second. It can ...

Page 15

Figure 8. Back-up mode alarm waveforms PFD (max) V PFD (min ABE, AFE bit in Interrupt Register AF bit in Flags Register IRQ/FT 3.5 Calibrating the clock The M48T37Y/V is driven by a quartz controlled ...

Page 16

Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a ...

Page 17

The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register or an edge transition (low to high / high to low) on the WDI pin occurs. The time-out period then starts over. The watchdog timer is ...

Page 18

Additionally battery low is indicated, data integrity should be verified upon ...

Page 19

Figure 9. Supply voltage protection V CC Figure 10. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 –10 Figure 11. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION V CC ...

Page 20

... Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 20/29 Parameter Grade 1 Grade 6 ® SNAPHAT Off, CC SOIC M48T37Y M48T37V M48T37Y M48T37V Value Unit °C – °C – °C –55 to 150 °C 260 °C –0 –0.3 to 4.6 V – ...

Page 21

... Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC testing load circuit 1. 50pF for M48T37V. Note: Excluding open-drain output pins Table 10. Capacitance Symbol C IN ...

Page 22

... 2.1mA 10mA –1mA 2 70°C or –40 to 85° 4.5 to 5.5V or 3.0 to 3.6V (except where A CC resistor. tFB tRB tDR DON'T CARE HIGH-Z M48T37V –100 Unit Min Max ±1 ±1 µA ±1 ±1 µ 0.8 –0.3 0 ...

Page 23

... CC (max) V Rise Time CC Rise Time 70°C or –40 to 85° may cause corruption of RAM data FB (1) Parameter M48T37Y M48T37V M48T37Y M48T37V Grade 1 Grade 70°C or –40 to 85° Min Max 300 200 = 4.5 to 5.5V or 3.0 to 3.6V (except where ...

Page 24

Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...

Page 25

Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data Symbol Typ ...

Page 26

Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mechanical data Symbol Typ ...

Page 27

Part numbering Table 17. Ordering information scheme Example: Device type M48T Supply voltage and write protect voltage 37Y = V = 4.5 to 5.5V 37V = V = 3.0 to 3.6V Speed –70 = 70ns ...

Page 28

Revision history Table 19. Document revision history Date Version Dec-1999 1.0 First Issue From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns 07-Feb-2000 2.0 speed class identifier changed 11-Jul-2000 2 19-Jun-2001 3.0 Reformatted; added ...

Page 29

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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