M48T37Y-70MH1E STMicroelectronics, M48T37Y-70MH1E Datasheet - Page 10

• Manufacturer Part Number: M48T37Y-70MH1E
• Description: IC TIMEKPR NVRAM 256KBIT5V 44SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37Y-70MH1E

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Bus Type: Parallel
• User Ram: 32KB
• Operating Supply Voltage (typ): 5V
• Package Type: SOH
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 44
• Mounting: Surface Mount
• Memory Configuration: 32K X 8
• Nvram Features: RTC
• Interface Type: Parallel
• Access Time: 70ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 44
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2854-5; M48T37Y-70MH1

Operation modes
2.2
10/30
WRITE mode
The M48T37Y/V is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; however, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
Figure 5.
Figure 6.
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
WRITE enable controlled, WRITE AC waveform
Chip enable controlled, WRITE AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
Doc ID 7019 Rev 9
tWLQZ
EHAX
WHDX
from chip enable or t
tAVWH
tAVEH
afterward. G should be kept high during WRITE
tWLWH
WLQZ
VALID
tAVAV
VALID
tAVAV
tELEH
after W falls.
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
from WRITE enable prior
tEHDX
M48T37Y, M48T37V
DVWH
tWHQX
tEHAX
tWHAX
prior to the
AI00927
AI00926