M48T37Y-70MH1E STMicroelectronics, M48T37Y-70MH1E Datasheet - Page 18

• Manufacturer Part Number: M48T37Y-70MH1E
• Description: IC TIMEKPR NVRAM 256KBIT5V 44SOH
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T37Y-70MH1E

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-SOH
• Bus Type: Parallel
• User Ram: 32KB
• Operating Supply Voltage (typ): 5V
• Package Type: SOH
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 44
• Mounting: Surface Mount
• Memory Configuration: 32K X 8
• Nvram Features: RTC
• Interface Type: Parallel
• Access Time: 70ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 44
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2854-5; M48T37Y-70MH1

Clock operations
3.9
Note:
3.10
3.11
18/30
Battery low flag
The M48T37Y/V automatically performs periodic battery voltage monitoring upon power-up.
The battery low flag (BL), bit D4 of the flags register 7FF0h, will be asserted high if the
SNAPHAT
active until completion of battery replacement and subsequent battery low monitoring tests
during the next power-up sequence.
If a battery low is generated during a power-up sequence, this indicates the battery voltage
is below 2.5 V (approximately), which may be insufficient to maintain data integrity. Data
should be considered suspect and verified as correct. A fresh battery should be installed.
The SNAPHAT top may be replaced while V
This will cause the clock to lose time during the interval the battery/crystal is removed.
Battery monitoring is a useful technique only when performed periodically. The M48T37Y/V
only monitors the battery when a nominal V
which require extensive durations in the battery back-up mode should be powered-up
periodically (at least once every few months) in order for this technique to be beneficial.
Additionally, if a battery low is indicated, data integrity should be verified upon power-up via
a checksum or other technique.
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT (see
Table 7.
1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
V
I
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
CC
Initial power-up
(Battery attach for SNAPHAT
Subsequent power-up / RESET
Power-down
CC
transients, including those produced by output switching, can produce voltage
noise and negative going transients
9) is recommended in order to provide the needed filtering.
®
Condition
(4)
battery is found to be less than approximately 2.5 V. The BL flag will remain
Default values
®
)
(2)
(3)
Doc ID 7019 Rev 9
W
0
0
0
CC
CC
that drive it to values below V
bus. These transients can be reduced if
CC
CC
R
0
0
0
is applied to the device. Thus applications
is applied to the device.
FT
0
0
0
CC
AFE
0
0
1
bus. The energy stored in the
Table
ABE
7).
0
0
1
M48T37Y, M48T37V
SS
by as much as
Watchdog
register
0
0
0
(1)