ISL12027IB27AZ Intersil, ISL12027IB27AZ Datasheet - Page 27

• Manufacturer Part Number: ISL12027IB27AZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12027IB27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Outline Drawing
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
6.40
0.20 C BA
4.40 ±0.10
3
SEATING
PLANE
C
TYPICAL RECOMMENDED LAND PATTERN
(0.65 TYP)
0.10 C
4
(5.65)
ID MARK
PIN 1
H
C L
TOP VIEW
SIDE VIEW
27
8
1
2
3.0 ±0.5
4
0.65
0.25 +0.05/-0.06
5
4
0.10
0.05
A
(0.35 TYP)
C B A
PACKAGE BODY
(1.45)
B
OUTLINE
ISL12027, ISL12027A
1.20 MAX
6
NOTES:
0.90 +0.15/-0.10
2. Dimension does not include mold flash, protrusions or
3. Dimension does not include interlead flash or protrusion.
4. Dimensions are measured at datum plane H.
6. Dimension on lead width does not include dambar protrusion.
7. Conforms to JEDEC MO-153, variation AC. Issue E
1. Dimensions are in millimeters.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 per side.
Interlead flash or protrusion shall not exceed 0.15 per side.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
Dimensions in (
SEE DETAIL "X"
0.15 MAX
0.05 MIN
0.09-0.20
) for Reference Only.
DETAIL "X"
END VIEW
1.00 REF
GAUGE
PLANE
0.60 ±0.15
0°-8°
August 12, 2010
0.25
FN8232.8