ISL12029IB27AZ Intersil, ISL12029IB27AZ Datasheet - Page 22

• Manufacturer Part Number: ISL12029IB27AZ
• Description: IC RTC/CALENDAR EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IB27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It should be noted, that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
Random read operations allow the master to access any
location in the ISL12029. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 25 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 25. The ISL12029 then goes
into standby mode after the stop and all bus activity will be
SIGNALS FROM
SIGNALS FROM
SIGNALS FROM
THE MASTER
SIGNALS FROM
SDA BUS
THE SLAVE
THE MASTER
SDA BUS
THE SLAVE
22
S
A
R
T
T
1
ADDRESS
ADDRESS
SLAVE
FIGURE 25. RANDOM ADDRESS READ SEQUENCE
SLAVE
1
1
A
C
K
FIGURE 26. SEQUENTIAL READ SEQUENCE
1
1
0
A
C
K
ISL12029, ISL12029A
0 0 0 0 0 0 0
DATA
ADDRESS 1
(1)
WORD
A
C
K
A
C
K
ADDRESS 0
ignored until a start is detected. This operation loads the new
address into the address counter. The next Current Address
Read operation will read from the newly loaded address.
This operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space the counter “rolls over” to the start of the
address space and the ISL12029 continues to output data
for each acknowledge received. Refer to Figure 26 for the
acknowledge and data transfer sequence.
DATA
(2)
WORD
A
C
K
A
C
K
S
T
A
R
T
(n IS ANY INTEGER GREATER THAN 1)
1
ADDRESS
(n - 1)
DATA
SLAVE
1
1
1
1
A
C
K
A
C
K
DATA
DATA
(n)
S
O
P
T
December 16, 2010
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FN6206.10