ISL12029IV27Z Intersil, ISL12029IV27Z Datasheet - Page 13

• Manufacturer Part Number: ISL12029IV27Z
• Description: IC RTC W/EEPROM 2.7V 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IV27Z

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit location.
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 15
and “Application Section” on page 23 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/F
The interrupts are enabled when either the AL1E or AL0E or
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
TABLE 3. BLOCK PROTECT BITS PARTITIONS
0
1
0
1
0
1
0
1
PROTECTED ADDRESSES
None (Default)
180
100
000
000
000
000
000
ISL12029
h
h
h
h
h
h
h
13
– 1FF
– 1FF
– 1FF
– 03F
– 07F
– 0FF
– 1FF
h
h
h
h
h
h
h
ARRAY LOCK
First 16 Pages
First 4 Pages
First 8 Pages
Upper 1/4
Upper 1/2
Full Array
Full Array
ISL12029, ISL12029A
None
OUT
).
both bits are set to ‘1’ and both the FO1 and FO0 bits are set to
0 (F
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/F
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/F
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/F
of the alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
Oscillator Compensation Registers
There are two trimming options.
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110 ppm of
total adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
FO1
- ATR - Analog Trimming Register
- DTR - Digital Trimming Register
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
0
0
1
1
OUT
OUT
disabled).
FO0
pin will be pulsed each time either alarm matches
0
1
0
1
OUT
output will now be pulsed each time an
Alarm output (F
OUTPUT FREQUENCY
OUT
32.768kHz
4096Hz
1Hz
will be pulsed for each
OUT
disabled)
December 16, 2010
FN6206.10