ISL12023IVZ Intersil, ISL12023IVZ Datasheet - Page 23

• Manufacturer Part Number: ISL12023IVZ
• Description: IC RTC/CLDR TEMP SNSR 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12023IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 15).
The ISL12023 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12023 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE ISL12023
FIGURE 16. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
23
START
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
START
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
1
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
DATA
ISL12023
0
WRITE
A
C
K
CHANGE
DATA
0 0 0 0
ADDRESS
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111” for the RTC registers and 1010111” for the User
SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 17).
BYTE
STABLE
DATA
A
C
K
8
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
S
T
O
P
June 24, 2009
FN6682.2