ISL12020MIRZ Intersil, ISL12020MIRZ Datasheet - Page 11

• Manufacturer Part Number: ISL12020MIRZ
• Description: IC RTC/CALENDAR TEMP SNSR 20-DFN
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12020MIRZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 12. BATTERY SWITCHOVER WHEN
FIGURE 13. BATTERY SWITCHOVER WHEN
The I
reduce power consumption. Aside from this, all RTC
functions are operational during battery-backup mode.
Except for SCL and SDA, all the inputs and outputs of
the ISL12020M are active during battery-backup mode
unless disabled via the control register.
The device Time Stamps the switchover from V
V
and t
power-down sequences occur before status is read, the
earliest V
most recent V
Temperature conversion and compensation can be
enabled in battery-backup mode. Bit BTSE in the BETA
register controls this operation, as described in “BETA
Register (BETA)” on page 19.
Power Failure Detection
The ISL12020M provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost
all power to the device (both V
Brownout Detection
The ISL12020M monitors the V
provides warning if the V
levels. There are six (6) levels that can be selected for
the trip level. These values are 85% below popular V
levels. The LVDD bit in the Status Register will be set to
“1” when brownout is detected. Note that the I
bus remains active unless the Battery V
reached.
BAT
V
V
V
V
V
TRIP
V
V
BAT
BAT
TRIP
DD
BAT
2
SB2V
DD
and V
C bus is deactivated in battery-backup mode to
- V
DD
registers respectively. If multiple V
BATHYS
V
BAT
TRIP
V
V
to V
BAT
BAT
BAT
to V
BAT
< V
> V
to V
DD
BATTERY-BACKUP
BATTERY-BACKUP
power-down time is stored and the
TRIP
TRIP
, and the time is stored in t
DD
DD
MODE
11
time is stored.
MODE
level drops below prescribed
DD
DD
and V
level continuously and
V
V
TRIP
BAT
TRIP
BAT
+ V
+ V
).
BATHYS
TRIPHYS
levels are
DD
2
3.0V
2.2V
2.2V
1.8V
DD
C serial
ISL12020M
SV2B
to
DD
Battery Level Monitor
The ISL12020M has a built in warning feature once the
Back Up battery level drops first to 85% and then to 75%
of the battery’s nominal V
voltage drops to between 85% and 75%, the LBAT85 bit
is set in the status register. When the level drops below
75%, both LBAT85 and LBAT75 bits are set in the status
register.
The battery level monitor is not functional in battery
backup mode. In order to read the monitor bits after
powering up V
which is set by setting the TSE bit to "1" (BETA register),
and then read the bits.
There is a Battery Time Stamp Function available. Once
the V
battery, the RTC time/date are written into the TSV2B
register. This information can be read from the TSV2B
registers to discover the point in time of the V
power-down. If there are multiple power-down cycles
before reading these registers, the first values stored in
these registers will be retained. These registers will hold
the original power-down value until they are cleared by
setting CLRTS = 1 to clear the registers.
The normal power switching of the ISL12020M is
designed to switch into battery-backup mode only if the
V
accept a wide range of backup voltages from many types
of sources while reliably switching into backup mode.
Note that the ISL12020M is not guaranteed to operate
with V
drop lower than this minimum, correct operation of the
device, especially after a V
guaranteed.
The minimum V
Below that, the SRAM may be corrupted when V
power resumes.
Real Time Clock Operation
The Real Time Clock (RTC) uses an integrated 32.768kHz
quartz crystal to maintain an accurate internal
representation of second, minute, hour, day of week,
date, month, and year. The RTC also has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24-hour or
AM/PM format. When the ISL12020M powers up after the
loss of both V
incrementing until at least one byte is written to the clock
register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing
Single Event or interrupt alarm mode is selected via the
IM bit. Note that when the frequency output function is
enabled, the alarm function is disabled.
The standard alarm allows for alarms of time, date,
day of the week, month, and year. When a time alarm
occurs in single event mode, the IRQ/F
pulled low and the alarm status bit (ALM) will be set
to “1”.
DD
power is lost. This will ensure that the device can
DD
BAT
is low enough to enable switchover to the
< 1.8V. If the battery voltage is expected to
DD
DD
BAT
, instigate a battery level measurement,
and V
to insure SRAM is stable is 1.0V.
BAT
BAT
, the clock will not begin
DD
level. When the battery
power-down cycle, is not
OUT
February 11, 2010
pin will be
DD
DD
FN6667.4