DS1682S Maxim Integrated Products, DS1682S Datasheet - Page 9

• Manufacturer Part Number: DS1682S
• Description: IC TIMEKEEPER ALARM ELAPSE 8SOIC
• Manufacturer: Maxim Integrated Products
• Type: Elapsed Time Counterr

Specifications of DS1682S

• Memory Size: 10B
• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

USER MEMORY
There are 10 bytes of user-programmable, EEPROM memory. Once the write-memory disable flag is set
to 1, the memory becomes read-only. User memory is not stored in EEPROM until an event becomes
inactive.
2-WIRE SERIAL DATA BUS
The DS1682 supports a bidirectional, 2-wire bus and data-transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data, a receiver. The device that controls
the message is called a master, and the devices controlled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions
must control the bus. The DS1682 operates as a slave on the 2-wire bus. Connections to the bus are made
through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):


Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high,
defines a START condition.
Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions are not limited, and are
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a
fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after it
receives each byte. The master device must generate an extra clock pulse, which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of
course, setup and hold times must be considered. A master must signal an end-of-data to the slave by not
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted as control signals.
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