X1226S8I Intersil, X1226S8I Datasheet - Page 9

• Manufacturer Part Number: X1226S8I
• Description: IC RTC/CALENDAR/4K EE 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of X1226S8I

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Bus Type: Serial (2-Wire, I2C)
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programmable Frequency Output Bits—FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 4 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
Table 4. Programmable Frequency Output Bits
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. Using a Citizen CFS-206 crystal
FO1
DTR2
0
0
1
1
0
0
0
0
1
1
1
1
DTR Register
FO0
0
1
0
1
DTR1
0
1
0
1
0
1
0
1
(average of 100 samples)
DTR0
0
0
1
1
0
0
1
1
Output Frequency
Alarm IRQ output
9
32.768kHz
Estimated frequency
4096Hz
1Hz
PPM
+10
+20
+30
-10
-20
-30
0
0
X1226
with different ATR bit combinations provides an esti-
mated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
The on-chip capacitance can be calculated as follows:
C
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application Section and Intersil’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing
clock/control register requires the following steps:
– Write a 02h to the Status Register to set the Write
– Write a 06h to the Status Register to set both the
– Write one to 8 bytes to the Clock/Control Registers
– Writing all zeros to the status register resets both the
– A read operation occurring between any of the previ-
ATR
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
WEL and RWEL bits.
ous operations will not interrupt the register write
operation.
= [(ATR value, decimal) x 0.25pF] + 11.0pF
any
of
the
nonvolatile
bits
May 8, 2006
of
FN8098.3
the