MCP3901A0-I/SS Microchip Technology, MCP3901A0-I/SS Datasheet - Page 35

• Manufacturer Part Number: MCP3901A0-I/SS
• Description: IC AFE 24BIT 64KSPS 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-I/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Supply Voltage Max: 5.5V
• Output Voltage: 0.4 V
• Output Power: 14 mW
• Input Voltage: 4.5 V to 5.5 V, 2.7 V to 5.5 V
• Switching Frequency: 4 MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• No. Of Channels: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP3901AO-I/SS; MCP3901AO-I/SS

FIGURE 6-5:
6.7
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter of the MCP3901 can be
set to loop on specific register sets. In this case, there
is only one control byte on SDI to start the
communication. The part stays within the same loop
until CS returns high.
This internal address counter allows the following
functionality:
• Read one ADC channel data continuously
• Read both ADC channel data continuously (both
• Read continuously the entire register map
• Read continuously each separate register
• Read continuously all configuration registers
• Write all configuration registers in one
FIGURE 6-6:
© 2009 Microchip Technology Inc.
ADC data can be independent or linked with
DRMODE settings)
communication (see
SDO
SCK
SDI
CS
DR
CS
SCK
SDI
SDO
MCU and MCP3901 Latch
Continuous Communication,
Looping On Address Sets
Bits on the Rising Edge
Data Transitions on
HI-Z
These bytes are not present when WIDTH=0 (16-bit mode)
CH0 ADC
the Falling Edge
ADDR/R
Upper byte
CH0 ADC
Device Write (SPI Mode 0,0 - Clock Idles Low).
Typical Continuous Read Communication.
Figure
Middle byte
A6 A5 A4 A3 A2 A1
CH0 ADC
6-6)
Lower byte
CH0 ADC
Upper byte
CH1 ADC
A0
R/W
Middle byte
CH1 ADC
D7
Lower byte
(ADDRESS) DATA
CH1 ADC
D6 D5 D4 D3 D2 D1
HI-Z
The STATUS/COM register contains the loop settings
for the internal address counter (READ<1:0>). The
internal address counter can either stay constant
(READ<1:0>=00) and read continuously the same
byte, or it can auto-increment and loop through the
register groups defined below (READ<1:0>=01),
register types (READ<1:0>=10) or the entire register
map (READ<1:0>=11).
Each channel is configured independently as either a
16-bit or 24-bit data word depending on the setting of
the corresponding WIDTH bit in the CONFIG1 register.
For continuous reading, in the case of WIDTH=0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH=0).
The following figure represents a typical continuous
read
(DRMODE<1:0>=00, READ<1:0>=10) for both WIDTH
settings. This configuration is typically used for power
metering applications.
Upper byte
CH0 ADC
D0
Middle byte
communication
CH0 ADC
D7
Lower byte
(ADDRESS + 1) DATA
CH0 ADC
D6 D5 D4 D3 D2 D1
Upper byte
CH1 ADC
Middle byte
with
CH1 ADC
D0
MCP3901
Lower byte
CH1 ADC
D7 OF (ADDRESS + 2) DATA
the
DS22192B-page 35
default
HI-Z
settings