MCP3901A0-I/SS Microchip Technology, MCP3901A0-I/SS Datasheet - Page 47

• Manufacturer Part Number: MCP3901A0-I/SS
• Description: IC AFE 24BIT 64KSPS 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-I/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Supply Voltage Max: 5.5V
• Output Voltage: 0.4 V
• Output Power: 14 mW
• Input Voltage: 4.5 V to 5.5 V, 2.7 V to 5.5 V
• Switching Frequency: 4 MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• No. Of Channels: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP3901AO-I/SS; MCP3901AO-I/SS

REGISTER 7-5:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7:6
bit 5
bit 4
bit 3:2
bit 1:0
READ<1>
R/W-1
READ: Address Loop Setting
11 = Address counter loops on entire register map
10 = Address counter loops on register TYPES (DEFAULT)
01 = Address counter loops on register GROUPS
00 = Address not incremented, continually read same single register
DR_LTY: Data Ready Latency Control
1 = “No Latency” Conversion, DR pulses after 3 DRCLK periods. (Default)
0 = Unsettled Data is available after every DRCLK period
DR_HIZn: Data Ready Pin Inactive State Control
1 = The data ready pin default state is a logic high when data is NOT ready
0 = The data ready pin default state is high impedance when data is NOT ready (Default)
DRMODE<1:0>: Data Ready Pin (DR) control
11 = Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin.
10 = Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are
01 = Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are
00 = Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging
DRSTATUS<1:0>: Data Ready Status
11 = ADC Channel 1 and Channel 0 data not ready (Default)
10 = ADC Channel 1 data not ready, ADC Channel 0 data ready
01 = ADC Channel 0 data not ready, ADC Channel 1 data ready
00 = ADC Channel 1 and Channel 0 data ready
READ<0>
R/W-0
not present on the pin.
not present on the pin.
ADC selection depends on the phase register and on the OSR (default).
STATUS AND COMMUNICATION REGISTER -> ADDRESS 0X09
W = Writable bit
‘1’ = Bit is set
DR_LTY
R/W-1
DR_HIZN
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DRMODE<1> DRMODE<0> DRSTATUS_
R/W-0
R/W-0
x = Bit is unknown
MCP3901
CH1
R-1
DS22192B-page 47
DRSTATUS_
CH0
R-1
bit 0