AD73311LARU Analog Devices Inc, AD73311LARU Datasheet - Page 27

• Manufacturer Part Number: AD73311LARU
• Description: IC ANALOG FRONT END 20-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73311LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-TSSOP
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

Interrupts
The AD73311L transfers and receives information over the
serial connection from the DSP’s SPORT. This occurs following
reset—during the initialization phase—and in both Data-Mode
and Mixed-Mode. Each transfer of data to or from the DSP can
cause a SPORT interrupt to occur. However, even in FSLB
configuration where serial transfers in and out of the DSP are
synchronous, it is important to note that Tx and Rx interrupts do
not occur at the same time due to the way that Tx and Rx inter-
rupts are generated internally within the DSP’s SPORT. This is
especially important in time-critical control loop applications where
it may be necessary to use Rx interrupts only, as the relative
positioning of the Tx interrupts relative to the Rx interrupts in a
single sample interval are not suitable for quick update of new
DAC positions.
Initialization
Following reset, the AD73311L is in its default condition,
which ensures that the device is in Control Mode and must be
programmed or initialized from the DSP to start conversions. As
communications between AD73311L and the DSP are interrupt
driven, it is usually not practical to embed the initialization codes
into the body of the initialization routine. It is more practical to
put the sequence of initialization codes in a data (or program)
memory buffer and to access this buffer with a pointer that is
updated on each interrupt. If a circular buffer is used, it allows
the interrupt routine to check when the circular buffer pointer
has wrapped around—at which point the initialization sequence
is complete.
In FSLB configurations, a single control word per codec per
sample period is sent to the AD73311L whereas in nonFSLB, it
is possible to initialize the device in a single sample period provided
the SCLK rate is programmed to a high rate. It is also possible
to use autobuffering, in which case an interrupt is generated when
the entire initialization sequence has been sent to the AD73311L.
Running the AD73311L with ADCs or DACs in Power-Down
The programmability of the AD73311L allows the user flexibility
in choosing which sections of the AD73311L need be powered
up. This allows better matching of the power consumption to the
application requirements as the AD73311L offers an ADC and
a DAC in any combination. The AD73311L always interfaces to
the DSP in a standard way regardless of whether the ADC or
DAC sections are enabled or disabled. Therefore, the DSP will
expect to receive an ADC samples per sample period and to
transmit two DAC samples per sample period. If the ADC is
disabled (in power-down), its sample value will be invalid. Like-
wise, a sample sent to a DAC that is disabled will have no effect.
There are two distinct phases of operation of the AD73311L:
initialization of the device via the control registers, and operation
of the converter sections of each codec. The initialization phase
involves programming the control registers of the AD73311L to
ensure the required operating characteristics such as sampling
rate, serial clock rate, I/O gain, etc. There are several ways in
which the DSP can be programmed to initialize the AD73311L.
These range from hard-coding a sequence of DSP SPORT Tx
register writes with constants used for the initialization words, to
putting the initialization sequence in a circular data buffer and
using an autobuffered transmit sequence.
Hard-coding involves creating a sequence of writes to the DSP’s
SPORT Tx buffer which are separated by loops or instructions
that idle and wait for the next Tx interrupt to occur as shown in
the code below.
The circular buffer approach can be useful if a long initialization
sequence is required. The list of initialization words is put into
the buffer in the required order.
.VAR/DM/RAM/CIRC init_cmds[8]; {Codec init sequence}
.VAR/DM/RAM stat_flag;
.INIT init_cmds:
and the DSP program initializes pointers to the top of the buffer
and puts the first entry in the DSP’s transmit buffer so it is
available at the first SDOFS pulse.
The DSP’s transmit interrupt is enabled.
At each occurrence of an SDOFS pulse, the DSP’s transmit
buffer contents are sent to the SDI pin of the AD73311L. This
also causes a subsequent DSP Tx interrupt which transfers the
initialization word, pointed to by the circular buffer pointer, to
the Tx buffer. The buffer pointer is updated to point to the next
unsent initialization word. When the circular buffer pointer wraps
around, which happens after the last word has been accessed, it
indicates that the initialization phase is complete. This can be
done “manually” in the DSP using a simple address check or auto-
buffered mode can be used to the complete transfer automatically.
txcdat: ar = dm(stat_flag);
b # 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 ,
b # 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 ,
b # 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 ,
b # 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ,
i3 = ^init_cmds;
ax0 = dm(i3,m1);
tx0 = ax0;
imask = b#0001000000;
ar = pass ar;
if eq rti;
ena sec_reg;
ax0 = dm (i3, m1);
tx0 = ax0;
ax0 = i3;
ay0 = ^init_cmds;
ar = ax0 - ay0;
if gt rti;
ax0 = 0x00;
dm (stat_flag) = ax0;
rti;
ax0
tx0
idle; {wait for tx register to send current word}
= b#1000000100000100;
= ax0;
l3 = %init_cmds;
AD73311L