AD73322LYR Analog Devices Inc, AD73322LYR Datasheet - Page 4

• Manufacturer Part Number: AD73322LYR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LYR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

AD73322L
SPECIFICATIONS
AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; DGND = AGND = 0 V, f
unless otherwise noted.
Operating temperature range as follows: A grade, T
Table 1.
Parameter
REFERENCE
INPUT AMPLIFIER
ANALOG GAIN TAP
ADC SPECIFICATIONS
REFCAP
REFOUT
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
Maximum Input Range at VIN
Nominal Reference Level at VIN
Absolute Gain
Gain Tracking Error
Signal-to-Noise and Distortion
Total Harmonic Distortion
Intermodulation Distortion
Idle Channel Noise Crosstalk
DC Offset
Power Supply Rejection Ratio
Absolute Voltage, VREFCAP
REFCAP TC
Typical Output Impedance
Absolute Voltage, V
Minimum Load Resistance
Maximum Load Capacitance
(0 dBm0)
PGA = 0 dB
PGA = 0 dB
PGA = 0 dB
ADC-to-DAC
ADC-to-ADC
REFOUT
1, 2
Min
1.08
1.08
−2.0
70
−20
MIN
A and Y Versions
= −40°C, T
Typ
1.2
50
130
1.2
1
100
±1.0
1.578
50
100
+1
−1
5
±1.0
1.0
0.5
1.578
−2.85
1.0954
−6.02
−0.7
±0.1
78
79
77.5
−86
−61
−72
−107
−92
−93
0
−65
Rev. A | Page 4 of 48
MAX
DMCLK
= +85°C; Y grade, T
Max
1.32
1.32
+0.5
−75
+20
= 16.384 MHz, f
Unit
V
ppm/°C
Ω
V
kΩ
pF
mV
V
kΩ
pF
Bits
%
µs
µs
V p-p
dBm
V p-p
dBm
dB
dB
dB
dB
dB
dB
dB
dBm0
dB
dB
dB
mV
dB
SAMP
Test Conditions/Comments
0.1 µF capacitor required from REFCAP to AGND2
Unloaded
Max output swing = (1.578/1.2) × VREFCAP
f
Gain step size = 0.0625
Output unloaded
Tap gain change of −FS to +FS
DAC unloaded
Measured differentially
Max input = (1.578/1.2) × VREFCAP
Measured differentially
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to −50 dBm0
Refer to Figure 9
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
0 Hz to f
300 Hz to 3400 Hz; f
PGA = 0 dB
PGA = 0 dB
ADC input signal level: 1.0 kHz, 0 dBm0
DAC input at idle
ADC1 input signal level: 1.0 kHz, 0 dBm0
ADC2 input at idle; input amplifiers bypassed
Input amplifiers included in input channel
PGA = 0 dB
Input signal level at AVDD and DVDD pins:
MIN
C
1.0 kHz, 100 mV p-p sine wave
= 32 kHz
= −40°C, T
= 8 kHz; T
SAMP
/2; f
MAX
A
SAMP
= T
= +105°C.
= 8 kHz
SAMP
SAMP
SAMP
MIN
to T
= 8 kHz, PUIA = 0
= 8 kHz, PUIA = 1
= 8 kHz
MAX
,