MCP3201-CI/SN Microchip Technology, MCP3201-CI/SN Datasheet - Page 23

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MCP3201-CI/SN

Manufacturer Part Number
MCP3201-CI/SN
Description
IC ADC 12BIT SINGLE CHAN 8SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of MCP3201-CI/SN

Package / Case
8-SOIC (0.154", 3.90mm Width)
Number Of Bits
12
Sampling Rate (per Second)
100k
Data Interface
Serial, SPI™
Number Of Converters
1
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Architecture
SAR
Conversion Rate
100 KSPs
Input Type
Voltage
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MCP3201-CI/SN
Manufacturer:
MICROCHIP
Quantity:
2 100
Part Number:
MCP3201-CI/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
MCP3201-CI/SN
0
MCP3201
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass
capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
connections to
DD
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See
Figure
6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
V
DD
Connection
Device 4
Device 1
Device 3
Device 2
FIGURE 6-4:
V
traces arranged in a
DD
‘Star’ configuration in order to reduce errors
caused by current return paths.
© 2008 Microchip Technology Inc.
DS21290E-page 23

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