CS5340-CZZ Cirrus Logic Inc, CS5340-CZZ Datasheet - Page 5

• Manufacturer Part Number: CS5340-CZZ
• Description: IC ADC AUD 101DB 200KHZ 16-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5340-CZZ

• Package / Case: 16-TSSOP
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 3.3 V or 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 90 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1544 - BOARD EVAL FOR CS5340 STEREO ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1081-5

4. Master/Slave and Speed Mode Selection
4.1
In the CS5333, the selection for Master or Slave mode operation is determined by a resistor pull-up/pull-
down on the SDATA pin (pin 4), as noted in Figure 1. If operating in Master mode, the Speed mode is
selected by the DIV pin (pin 8). If DIV is resistively pulled low, the CS5333 will enter into Base Rate mode
(Fs = 2 kHz to 50 kHz). If DIV is resistively pulled high to VL, the CS5333 will enter into High Rate mode
(Fs = 50 kHz to 100 kHz). If the CS5333 is operating in Slave mode, the Speed mode is auto-detected
and the DIV pin operates as an MCLK divide by two enable.
4.2
In the CS5340, Master or Slave mode operation and Speed mode is determined by the mode pins, M1
and M0 (pins 16 and 1 respectively), as shown in Table 3.
Please note that Base Rate mode is synonymous with Single Speed mode, and High Rate mode is syn-
onymous with Double Speed mode.
5. Digital Interface Format Select
5.1
The CS5333 supports both Left Justified and I
the DIF pin (pin 9). If this pin is held at a logic low upon startup, I
held at a logic high upon startup, Left Justified interface format will be selected.
5.2
The CS5340 also supports both Left Justified and I
by a resistor pull-up/pull-down on the SDOUT pin (pin 4). If this pin is resistively pulled low upon startup,
Left Justified interface format will be selected. If this pin is resistively pulled high to VL upon startup, I
interface format will be selected.
6. System Clocking
The clocking requirements for the CS5333 and CS5340 are the same for Master mode operation. How-
ever, in Slave mode operation the CS5340 only supports a subset of the clocking supported in the
CS5333. The CS5333 supports an MCLK/LRCK ratio of 256x, 384x, 512x, and 768x in Base Rate mode
and 128x, 192x, 256x and 384x in High Rate mode. The CS5340 cannot support ratios of 192x, 384x, or
768x. See Table 4. Due to the auto-speed mode detect circuitry implemented in the CS5340, not all sam-
ple rate ranges are supported in Slave mode. Please refer to the CS5340 datasheet for more information.
CS5333
CS5340
CS5333
CS5340
CS5333
CS5340
Device
Table 4. Supported MCLK/LRCK Ratios, Slave Mode Operation
M1 (Pin 16) M0 (Pin 1)
Double Speed
Speed Mode
Single Speed
Base Rate
0
0
1
1
High Rate
Table 3. CS5340 Mode Control
0
1
0
1
2
S digital interface formats. The interface is selectable by
Master, Single Speed Mode
Master, Double Speed Mode
Master, Quad Speed Mode
Slave, All Speed Modes
2
S digital interface formats. The interface is selectable
Supported MCLK/LRCK Ratios
Mode
256, 384, 512, 768
128, 192, 256, 384
2
S interface format will be selected. If
256, 512
128, 256
AN249
2
S
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