CS5523-ASZ Cirrus Logic Inc, CS5523-ASZ Datasheet
CS5523-ASZ
Specifications of CS5523-ASZ
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CS5523-ASZ Summary of contents
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... The ADCs come as either (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- mentation amplifier. To permit selectable input spans of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V, the ADCs include a PGA (programmable gain amplifier) ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8 5 ...
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Unipolar/Bipolar Bit ............................................................................. 28 2.2.8 Configuration Register ........................................................................................ 28 2.2.8.1 Chop Frequency Select ...................................................................... 28 2.2.8.2 Conversion/Calibration Control Bits .................................................... 28 2.2.8.3 Power Consumption Control Bits ........................................................ 28 2.2.8.4 Charge Pump Disable ......................................................................... 29 2.2.8.5 Reset System Control Bits ...
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... Figure 6. Input Models for AIN+ and AIN- pins, >100 mV input ranges ........................................ 14 Figure 7. Input Ranges Greater than 5 V ...................................................................................... 16 Figure 8. Input Model for VREF+ and VREF- Pins........................................................................ 16 Figure 9. CS5523/24 Register Diagram ........................................................................................ 17 Figure 10. Command and Data Word Timing................................................................................ 25 Figure 11. Self Calibration of Offset (Low Ranges)....................................................................... 32 Figure 12 ...
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CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) Parameter Accuracy Resolution Linearity ...
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ANALOG CHARACTERISTICS Parameter Analog Input Common Mode + Signal on AIN+ or AIN- NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = NBV = AGND ...
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TYPICAL RMS NOISE, CS5521/23 Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 12) 50.4 84.5 (Note 12) 70.7 101.1 (Note 12) 84.6 Notes: 10. Wideband noise aliased into the ...
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TYPICAL RMS NOISE, CS5522/24/28 Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 16) 50.4 84.5 (Note 16) 70.7 101.1 (Note 16) 84.6 Notes: 14. Wideband noise aliased into the ...
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V DIGITAL CHARACTERISTICS See Notes 2 and 18.)) Parameter High-level Input Voltage All Pins Except XIN and SCLK Low-level Input Voltage All Pins Except XIN and SCLK High-level Output Voltage All Pins Except CPD and SDO (Note 19) Low-level ...
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DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full-scale Step) RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 20. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS Parameter DC ...
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SWITCHING CHARACTERISTICS Levels: Logic Logic 1 = VD+; C Parameter Master Clock Frequency External Clock or Internal Oscillator (CS5522/24/28) Master Clock Duty Cycle Rise Times Any Digital Input Except SCLK Fall Times Any Digital Input Except ...
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Figure 1. Continuous Running SCLK Timing (Not to Scale ...
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... Analog-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) perfor- mance. The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight- channel (CS5528) devices, and include a low input current, chopper-stabilized instrumentation ampli- fier. To permit selectable input spans of 25 mV, 55 mV, 100 mV ...
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Instrumentation Amplifier The instrumentation amplifier is chopper stabilized and is activated any time conversions are performed with the low-level input ranges, ≤100 mV. The am- plifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin CS5521/22/23/24/28 ...
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Analog Input Span Considerations The CS5521/22/23/24/28 is designed to measure full-scale ranges of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V. Other full scale values can be ac- commodated by performing a system calibration ...
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... Figure 9 depicts a block diagram of the on-chip controller’s internal registers for the CS5523/24. Each of the converters has 24-bit registers to func- tion as offset and gain calibration registers for each channel. The converters with two channels have ...
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... Table 2 can be used to decode all valid commands (the first 8 bits into the serial port). 4 (24 Gain 1 Setup 1 Setup 2 Gain 2 Setup 3 Setup 4 Gain 3 Setup 5 Setup 6 Gain 4 Setup 7 Setup Configuration Latch Outputs Channel Select Output Word Rate PGA Selection Unipolar/Bipolar Figure 9. CS5523/24 Register Diagram CS5521/22/23/24/ DATA FIFO SDO 17 ...
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System Initialization When power to the CS5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 kHz oscillator has started and a counter- timer elapses. Due to the high Q of the 32.768 kHz crystal, ...
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... Read from selected register. 000 Reserved 001 Offset Register 010 Gain Register 011 Configuration Register 101 Channel Set-up Registers - register is 48-bits long for CS5521/22 - register is 96-bits long for CS5523/24 - register is 192-bits long for CS5528 110 Reserved 111 Reserved CSRP0 CC2 CC1 ...
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... CS[2:0] (Channel Select Bits) 000 Gain Register 1(All devices) 001 Gain Register 2 (All devices) 010 Gain Register 3 (CS5523/24/28 only) 011 Gain Register 4 (CS5523/24/28 only) 100 Gain Register 5 (CS5528 only) 101 Gain Register 6 (CS5528 only) 110 Gain Register 7 (CS5528 only) 111 Gain Register 8 (CS5528 only) ...
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... CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. R/W (Read/Write) 0 Write to selected register ...
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... Setup 3 (All devices) 0011 Setup 4 (All devices) 0100 Setup 5 (CS5523/24/28) 0101 Setup 6 (CS5523/24/28) 0110 Setup 7 (CS5523/24/28) 0111 Setup 8 (CS5523/24/28) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 ...
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... Setup 3 (All devices) 0011 Setup 4 (All devices) 0100 Setup 5 (CS5523/24/28 only) 0101 Setup 6 (CS5523/24/28 only) 0110 Setup 7 (CS5523/24/28 only) 0111 Setup 8 (CS5523/24/28 only) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) ...
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SYNC1 D7(MSB Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port ...
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Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port’s registers. CS (Chip Select) is the control ...
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... Reading/Writing the Channel-Setup Reg- isters The CS5521/22 have two 24-bit channel-setup reg- isters (CSRs). The CS5523/24 have four CSRs, and the CS5528 has eight CSRs (refer to Table 3 for more detail on the CSRs). These registers are ac- cessed in conjunction with the depth pointer bits in the configuration register ...
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... R Select physical channel 1 (All devices) 001 Select physical channel 2(All devices) 010 Select physical channel 3 (CS5523/24/28 only) 011 Select physical channel 4 (CS5523/24/28 only) 100 Select physical channel 5 (CS5528 only) 101 Select physical channel 6 (CS5528 only) 110 Select physical channel 7 (CS5528 only) ...
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Latch Outputs The A1-A0 pins mimic the latch output, D23/D11- D22/D10, bits of the channel-setup registers. A1-A0 can be used to control external multiplexers and oth- er logic functions outside the converter. The outputs can sink or source at ...
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CS5522/24/28 typically consume 9.0 mW. The CS5521/23 typically consume 6.0 mW. The low- power mode is an alternate mode in the CS5522/24/28 that reduces the consumed power to 5.5 mW entered by setting bit D8 (the low- power ...
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D23(MSB) D22 D21 D20 NU NU CFS1 CFS0 D11 D10 D9 PSS PD PS/R LPM BIT NAME D23-D22 Not Used, NU D21-D20 Chop Frequency Select, CFS1-CFS0 D19 Not Used, NU D18 Multiple Conversion, MC D17 Loop, LP D16 Read Convert, ...
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Calibration The CS5521/22/23/24/28 offer four different cali- bration functions including self calibration and sys- tem calibration. However, after the devices are reset, the converter is functional and can perform measurements without being calibrated. In this case, the converter will ...
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AIN- pin must be at the proper com- mon-mode voltage as specified in ‘Common Mode +Signal AIN+/-’ specification in the Analog Input section (if AIN- = ...
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In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the ‘System Calibration Specifications’ in ANALOG CHARACTERISTICS system gain calibration is performed the ...
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... While reading, note that the CS5521/22 have a FIFO which is four words deep. The CS5523/24 have a FIFO which is eight words deep and the CS5528 has a FIFO which is sixteen -22 decimal) ...
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Further note that the type of conversion(s) performed and the way to access the resulting data from the FIFO is determined by the MC (multiple conversion), the LP (loop), the RC (read convert), and the DP (depth ...
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SDO line. If, during the first 8 SCLKs, "00000000" is provided on SDI, the converter will remain in this conversion mode, and continue to perform conversions on the selected Setup. To exit this conversion mode, "11111111" must be provid- ed ...
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Repeated Multiple-Setup Conversions without Wait ( this conversion mode, the ADC will repeatedly perform conversions, referencing multiple Setups. The CSRP bits in the command word are ignored in this mode. ...
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SCLKs for each Setup referenced are required to read the conversion words from the data FIFO. The first 8 SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter consist of the data words of each Setup ...
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SD0. After ‘1111 1111’ is provided, 24 additional SCLKs are required to transfer the last 3 bytes of conversion data before the serial port will return to the command mode. Example 3: The configuration register has the following bits as ...
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Once the CSRs are programmed, repeated conver- sions Setups can be performed by is- suing only one command byte. 5) The single conversion mode also requires only one command, but whenever ...
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... CI (Channel Indicator Bits) [1:0] These bits indicate which physical input channel was converted. 00 Physical Channel 1 (CS5521/23 only) 01 Physical Channel 2 (CS5521/23 only) 10 Physical Channel 3 (CS5523 only) 11 Physical Channel 4 (CS5523 only) DS317F4 D18 D17 D16 D15 ...
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Digital Filter The CS5521/22/23/24/28 have eight different lin- ear phase digital filters which set the output word rates (OWRs) shown in Table 3. These rates as- sume that XIN is 32.768 kHz. Each of the filters has a magnitude ...
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Power Supply Arrangements The CS5521/22/23/24/28 A/D converters are de- signed to operate from a single +5 V analog supply and a single + digital supply. A -2.1 V supply is usually generated from the charge ...
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Figure 22. CS5522 Configured for ground-referenced Unipolar Signals + alo ...
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Charge Pump Drive Circuits The CPD (Charge Pump Drive) pin of the converter can be used with external components (shown in Figure 21) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to ...
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The converter input ranges are specified with a voltage reference of 2.5 V. The device can be op- erated ...
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Note that while the RS bit is set to ‘1’ all other register bits in the ADC will be reset to their default state, and the RS bit must be set to ‘0’ for normal operation of the ...
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... SDO SERIAL DATA OUT 9 12 XIN XOUT CRYSTAL OUT 10 11 AGND VREF+ VOLTAGE REFERENCE INPUT 1 24 VA+ VREF- VOLTAGE REFERENCE INPUT 2 CS5523 23 CS5524 AIN1+ AIN2+ DIFFERENTIAL ANALOG INPUT 3 22 AIN1- AIN2- DIFFERENTIAL ANALOG INPUT 4 21 AIN3+ AIN4+ DIFFERENTIAL ANALOG INPUT 5 20 AIN3- ...
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Clock Generator XIN; XOUT - Crystal In; Crystal Out. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) ...
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NBV - Negative Bias Voltage. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier and coarse/fine charge buffers. May be tied to AGND if AIN+ and AIN- inputs are centered around +2 ...
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint ...
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... Plastic DIP CS5522-AS 20-pin 0.2" Plastic SSOP CS5522-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5523-AS 24-pin 0.2" Plastic SSOP CS5523-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) CS5524-AP 24-pin 0.3" Plastic DIP CS5524-AS 24-pin 0.2" Plastic SSOP CS5524-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) CS5528-AS 24-pin 0.2" ...
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PACKAGE DIMENSION DRAWINGS 20 PIN PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 0.980 E 0.300 E1 0.240 e 0.090 eA 0.280 ...
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PIN SKINNY PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 1.230 E 0.300 E1 0.240 e 0.090 eA 0.280 eB 0.300 eC ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.272 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...