AD7192BRUZ Analog Devices Inc, AD7192BRUZ Datasheet
AD7192BRUZ
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AD7192BRUZ Summary of contents
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FEATURES RMS noise 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time ...
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AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 7 Circuit and Timing Diagrams ..................................................... 7 Absolute ...
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SPECIFICATIONS 5. 2 5.25 V, AGND = DGND = 0 V; REFINx(+) = unless otherwise noted. A MIN MAX Table 1. ...
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AD7192 Parameter AD7192B External Clock @ 50 Hz 120 120 @ 60 Hz 120 3 Sinc Filter Internal Clock @ 50 Hz ...
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Parameter AD7192B Average Reference Input Current ±0.03 Drift ±1.3 Normal Mode Rejection 2 Same as for analog inputs Common-Mode Rejection 100 Reference Detect Levels 0.3 0.6 TEMPERATURE SENSOR Accuracy ±2 Sensitivity 2815 BRIDGE POWER-DOWN SWITCH Allowable ...
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AD7192 Parameter AD7192B 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS Zero-Scale Calibration Limit −1.05 × FS Input Span 0.8 × FS 2.1 × POWER REQUIREMENTS Power Supply Voltage AV − AGND 3/5. − DGND ...
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TIMING CHARACTERISTICS 5. 2 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic Table 2. Parameter Limit at ...
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AD7192 DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AV to AGND −0 +6 AGND −0 +6 AGND to DGND −0 +0.3 V ...
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AD7192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 ...
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Pin No. Mnemonic Description 13 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 pseudodifferential input when used with AINCOM. 14 AIN4 Analog Input. ...
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AD7192 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,884 8,388,882 8,388,880 8,388,878 8,388,876 8,388,874 8,388,872 8,388,870 8,388,868 8,388,866 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, REF DD Gain = 128, Chop ...
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V (V) IN Figure 12. INL (Gain = –5 –10 –15 –20 –0.03 –0.02 –0.01 0 0.01 V (V) ...
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AD7192 RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc In addition, the AD7192 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7192 for some ...
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SINC CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) 1023 4.7 639.4 640 7.5 400 480 10 300 ...
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AD7192 4 SINC CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) 1023 1.175 1702 640 1.875 1067 480 2.5 800 96 12.5 160 80 15 ...
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SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) 1023 1.56 1282 640 2.5 800 480 3.33 600 96 16.6 120 80 20 100 ...
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AD7192 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages. In the following descriptions, “set” implies a Logic 1 state and “cleared” implies a Logic 0 state, unless ...
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STATUS REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be ...
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AD7192 Table 17. Mode Register Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7192 (see Table 18). MR20 DAT_STA This bit enables the transmission ...
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Table 18. Operating Modes MD2 MD1 MD0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in ...
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AD7192 Table 19. Configuration Register Bit Designations Bit Location Bit Name Description CON23 CHOP Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the ...
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Table 20. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 DATA REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x000000) The conversion result from the ADC is ...
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AD7192 GPOCON REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the ...
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ADC CIRCUIT INFORMATION 5V IN+ OUT+ OUT– IN– OVERVIEW The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those ...
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AD7192 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (Hz) 3 Figure 20. Sinc Filter Response (50 Hz Output Data Rate) 4 The sinc filter provides 50 Hz (±1 Hz) rejection in ...
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Hz/60 Hz Rejection Normal mode rejection is one of the main functions of the digital filter. With chop disabled rejection is obtained when the output data rate is set to 50 Hz, and 60 Hz rejection is ...
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AD7192 (sinc filter rejection is no longer achieved. The ADC must operate with an output data rate of 12 obtain 50 Hz rejection when zero latency is enabled. To obtain simultaneous 50 ...
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However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The ...
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AD7192 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7192 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also ...
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Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7192 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to ...
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AD7192 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7192 has two differential/four pseudodifferential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into ...
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MCLK2 pin, and the MCLK1 pin can be left floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs ...
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AD7192 RESET The circuitry and serial interface of the AD7192 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, ...
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ENABLE PARITY The AD7192 also has a parity check function on chip that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is ...
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AD7192 4.75 V, the gain error post internal full-scale calibration is 0.005%, typically. When AV is less than 4.75 V, the CLK_DIV bit must be set DD when performing internal full-scale calibrations. The accuracy of the internal full-scale calibration is ...
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APPLICATIONS INFORMATION The AD7192 provides a low-cost, high resolution analog-to- digital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial ...
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... AD7192 OUTLINE DIMENSIONS 0.15 0.05 ORDERING GUIDE Model Temperature Range AD7192BRUZ 1 –40°C to +105°C 1 AD7192BRUZ-REEL –40°C to +105° RoHS Compliant Part. 7.90 7.80 7. 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.30 0.20 SEATING 0.19 PLANE ...
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NOTES Rev Page AD7192 ...
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AD7192 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07822-0-5/09(A) Rev Page ...