AD7799BRUZ Analog Devices Inc, AD7799BRUZ Datasheet - Page 14

• Manufacturer Part Number: AD7799BRUZ
• Description: IC ADC 24BIT SIG-DEL 3CH 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7799BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 470
• Number Of Converters: 1
• Power Dissipation (max): 2.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 470SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7799EBZ - BOARD EVALUATION FOR AD7799
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7798/AD7799
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799)
The status register is an 8-bit, read-only register. To access the status register, the user must write to the communication register, select the
next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream.
The number in parentheses indicates the power-on/reset default status of the bit.
SR7
RDY(1)
Table 11. Status Register Bit Designations
Bit Location
SR7
SR6
SR5
SR4
SR3
SR2 to SR0
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and low-side power switch. Table 12 outlines the bit designations for the mode register. MR0 through MR15
indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default status of that bit. A write to the mode register resets the modulator and filter
and sets the RDY bit.
MR15
MD2(0)
MR7
0(0)
Table 12. Mode Register Bit Designations
Bit Location
MR15 to MR13
MR12
MR11 to MR4
MR3 to MR0
Bit Name
RDY
ERR
NOREF
0
0/1
CH2 to CH0
SR6
ERR(0)
0
Bit Name
MD2 to MD0
PSW
FS3 to FS0
MR14
MD1(0)
MR6
0(0)
Description
Ready Bit. Cleared when data is written to the data register. Set after the data register is read or after a period
of time before the data register is updated with a new conversion result to indicate to the user not to read the
conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is
indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring
the ADC for conversion data.
Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the
data register is clamped to all 0s or all 1s. Error sources include overrange and underrange. Cleared by a write
operation to start a conversion.
No Reference Bit. Set to indicate that the reference (REFIN) is at a voltage below a specified threshold. When
NOREF is set, conversion results are clamped to all 1s. Cleared to indicate that a valid reference is applied to
the reference pins. The NOREF bit is enabled by setting the REF_DET bit in the configuration register to 1.
This bit is automatically cleared.
This bit is automatically cleared on the AD7798 and automatically set on the AD7799.
These bits indicate which channel is being converted by the ADC.
SR5
NOREF(0)
Description
Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (see Table 13).
Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can
sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down
mode, the power switch is opened.
These bits must be programmed with a Logic 0 for correct operation.
Filter Update Rate Select Bits (see Table 14).
MR13
MD0(0)
MR5
0(0)
SR4
0(0)
MR12
PSW(0)
MR4
0(0)
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SR3
0/1
MR11
MR3
FS3(1)
0(0)
SR2
CH2(0)
MR10
0(0)
MR2
FS2(0)
SR1
CH1(0)
MR9
0(0)
MR1
FS1(1)
SR0
CH0(0)
MR8
0(0)
MR0
FS0(0)