AD7651ASTZ Analog Devices Inc, AD7651ASTZ Datasheet - Page 21
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AD7651ASTZ
Manufacturer Part Number
AD7651ASTZ
Description
IC ADC 16BIT 100KSPS 48-LQFP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet
1.AD7651ASTZ.pdf
(28 pages)
Specifications of AD7651ASTZ
Data Interface
Serial, Parallel
Number Of Bits
16
Sampling Rate (per Second)
100k
Number Of Converters
1
Power Dissipation (max)
45mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
16bit
Input Channel Type
Pseudo Differential
Supply Voltage Range - Analogue
4.75V To 5.25V
Supply Voltage Range - Digital
2.7V To 5.25V,
Sampling Rate
100kSPS
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7651CBZ - BOARD EVALUATION FOR AD7651
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7651ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
MASTER SERIAL INTERFACE
Internal Clock
The AD7651 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7651 also
generates a SYNC signal to indicate to the host when the serial data
is valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on the RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figure 32
and Figure 33 show detailed timing diagrams of these two modes.
CS, RD
CS, RD
SDOUT
CNVST
SDOUT
CNVST
BUSY
SYNC
SCLK
BUSY
SYNC
SCLK
t
16
t
3
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
t
t
14
15
16
t
t
t
14
15
29
t
17
X
t
t
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
18
22
EXT/INT = 0
t
EXT/INT = 0
1
t
D15
3
X
t
t
1
20
22
t
19
t
21
t
20
D14
t
D15
2
23
1
t
19
t
18
Rev. 0 | Page 21 of 28
RDC/SDIN = 0
RDC/SDIN = 1
D14
t
2
t
21
3
23
t
28
3
Usually, because the AD7651 has a longer acquisition phase than
the conversion phase, the data is read immediately after conversion.
This makes the Master Read After Conversion the most recom-
mended serial mode when it can be used. In this mode, it should be
noted that unlike in other modes, the BUSY signal returns LOW
after the 16 data bits are pulsed out and not at the end of the
conversion phase, which results in a longer BUSY width.
In the Read During Conversion mode, the serial clock and data
toggle at appropriate instants, which minimize potential feed-
through between digital activity and critical conversion decisions
INVSCLK = INVSYNC = 0
14
D2
INVSCLK = INVSYNC = 0
14
D2
15
D1
15
D1
16
t
24
16
t
30
D0
t
D0
24
02964-0-015
02964-0-016
t
t
t
t
t
t
25
26
27
25
26
27
AD7651