CS5566-ISZ Cirrus Logic Inc, CS5566-ISZ Datasheet
CS5566-ISZ
Specifications of CS5566-ISZ
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CS5566-ISZ Summary of contents
Page 1
... AIN in- puts and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5566 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture ...
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... Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Using the CS5566 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. PIN DESCRIPTIONS 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 30 8 ...
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... Figure 4. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Power Consumption vs. Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. CS5566 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. CS5566 Configured Using a Single 5V Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10. CS5566 DNL Plot Figure 11. Spectral Performance Figure 12 ...
Page 4
... Bipolar mode unless otherwise stated. (Note 1) (Note 2) (Note 2) (Note 2) 200 Hz, -0.5 dB Input 200 Hz, -0.5 dB Input -0.5 dB Input, 200 Hz -60 dB Input, 200 Hz (Note 3) Unipolar Bipolar AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V 4.096) ÷ 16,777,216 = 488 nV. CS5566 = 25°C. A Min Typ Max Unit ±%FS - 0.0005 - - ±0.1 - LSB ...
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... V1+ = V2+ = +2.5 V, ±5%; V1- = (CONTINUED) A Figure 8. (Note 5) VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREF (Note Normal Operation Buffers On (Note 6) Buffers Off Sleep (SLEEP = 0) (Note 7) V1+ , V2+ Supplies V1-, V2- Supplies for more details. CS5566 Min Typ Max 4.2 2.4 4.096 - 0 0 ...
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... External Clock f clk t res Internal Oscillator t wup External Clock t cpw (Note 8) t scn t scn t bus (Note 9) t buh t con t con IDLE 1182 - 1186 MCLKs 1600 - 1604 MCLKs Figure 1. Converter Status (Not to scale) CS5566 Min Typ Max 0 240 - - 3084 - 1182 ...
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... SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor. 12. SCLK = MCLK/2. MCLK RDY SCLK(o) SDO MSB Figure 2. SSC Mode - Read Timing, CS remaining low (Not to Scale) DS806PP1 3/25/08 (CONTINUED) Symbol Min Pulse Width (low) t 100 3 Pulse Width (high) 100 MSB–1 CS5566 Typ Max Unit -2 - MCLKs MCLKs t 5 LSB LSB+1 7 ...
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... SCLK = MCLK/2. MCLK RDY SCLK( SDO MSB Figure 3. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) 8 3/25/08 (CONTINUED) Symbol Min Pulse Width (low) t 100 8 Pulse Width (high) 100 MSB–1 CS5566 Typ Max Unit MCLKs MCLKs - - LSB+1 LSB DS806PP1 ...
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... RDY rising after SCLK falling 15. SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor. MCLK RDY SCLK( SDO Figure 4. SEC Mode - Continuous SCLK Read Timing (Not to Scale) DS806PP1 3/25/08 (CONTINUED) Symbol - - (Note 15 MSB CS5566 Min Typ Max Unit SCLK - LSB ns ...
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... The 160 MCLK group delay occurs during the 354 MCLK high-power period of a conversion cycle. See Section 3.2 Power Consumption 10 3/25/ MSB Symbol out Symbol (Note 16) - for more detail. CS5566 LSB Min Typ Max Unit - - 2 µ Min Typ ...
Page 11
... Minimum High-level Output Voltage: Maximum Low-level Output Voltage: DS806PP1 3/25/08 Guaranteed Limits Sym VL Min Typ 3.3 1.9 V 2.5 1.6 IH 1.8 1.2 3.3 V 2.5 IL 1.8 3.3 2.9 V 2.5 2.1 OH 1.8 1.65 3.3 V 2.5 OL 1.8 CS5566 Max Unit Conditions V 1.1 0. 0.36 0. 0.44 11 ...
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... V2+ V2- V1- V1+ V2- V2- (Note 18) VREF [VREF+] – [VREF-] Symbol [V1+] – [V1-] (Note 19 |V1-| ] (Note 20) - (Note 21 (AIN and VREF pins) V INA V IND T stg WARNING: CS5566 Min Typ Max 4.75 5.0 5.25 4.75 5.0 5. +2.375 +2.5 +2.625 +2.375 +2.5 +2.625 -2.375 -2.5 -2.625 -2.375 -2 ...
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... OVERVIEW The CS5566 is a 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The device is ca- pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion ...
Page 14
... Converter Operation The converter should be reset after the power supplies and voltage reference are stable. The CS5566 converts at 5 kSps when synchronously operated (CONV = VLR) from a 8.0 MHz master clock. Conversion is initiated by taking CONV low. A conversion lasts 1600 master clock cycles, but if CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to when a conversion actually begins ...
Page 15
... Power Consumption The power consumption of the CS5566 converter is a function of the conversion rate. the typical power consumption of the converter when operating from either MCLK = 8 MHz or MCLK = 4 MHz. The rate at which conversions are performed directly affects the power consumption. When the converter is powered but not converting idle state where its power consumption is about 11 mW ...
Page 16
... IC to the analog input. Adding a 50 ohm resistor on the external MCLK source significantly reduces this effect. 3.4 Voltage Reference The voltage reference for the CS5566 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is re- quired to achieve the specified performance. reference with either a single +5 V analog supply or with ±2.5 V. ...
Page 17
... The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5566. The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the A/D inputs while the resistors isolate the dynamic current from the amplifier ...
Page 18
... Typical Connection Diagrams The following figure depicts the CS5566 powered from bipolar analog supplies, +2.5 V and - 2 49 47pF +2.048 V 4.99k -2.048 V 4.99k +2.048 -2.048 V 49 47pF 4.99k 4.99k +2.5 V +4.096 Voltage Reference (NOTE 1) -2.5 V Figure 8. CS5566 Configured Using ± 2.5V Analog Supplies ...
Page 19
... The following figure depicts the CS5566 device powered from a single 5V analog supply. 49.9 2.048 V 47pF 4.548 V 2.5 V 4.99k +0.452 V +4.548 V 2.5 V +0.452 V 49.9 4.096 V 47pF 4.99k +5 V +4.096 Voltage Reference (NOTE 1) Figure 9. CS5566 Configured Using a Single 5V Analog Supply DS806PP1 3/25/08 4700pF ...
Page 20
... AIN & VREF Sampling Structures The CS5566 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher input impedance and therefore reduce the amount of drive current required from an external source. This helps minimize errors. The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is con- nected to the V1+ supply, the buffers will be enabled ...
Page 21
... Figure 14. Spectral Performance, - -20 -40 -60 -80 -100 -120 -140 -160 -180 0 1.5k 2k 2.5k Figure 16. Spectral Performance, -120 dB CS5566 277 Hz 32k Samples @ 5 kSps 500 1k 1.5k 2k Frequency (Hz) 277 Hz, -20 dB 32k Samples @ 5 kSps 500 1k 1.5k 2k Frequency (Hz) 277 Hz, -120 dB 32k Samples @ 5 kSps 500 1k 1.5k ...
Page 22
... The signal input for figure 15 is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. with a signal at about 2.6 microvolts peak to peak, or about 5 codes peak to peak. The CS5566 achieves superb performance with this small signal. ...
Page 23
... The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter attenuation is -0.0414 dB at 2.5 kHz when sampling at 5 kSps. Figure 20. Digital Filter Response (DC to 2.5 kHz) DS806PP1 3/25/08 -0.001646 kSps -0.00663 dB -0.0149 dB -0.0262 dB Frequency (Hz) CS5566 -0.0414 dB 23 ...
Page 24
... Serial Port The serial port on the CS5566 can operate in two different modes: synchronous self clock (SSC) mode & synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset and gain registers of the converter are to be read or written. The converter must be idle when reading or writing to the on-chip registers ...
Page 25
... Power Supplies & Grounding The CS5566 can be configured to operate with its analog supply operating from 5V, or with its analog sup- plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or 3.3V. Figure 8 on page 18 illustrates the device configured to operate from ±2.5V analog. ...
Page 26
... V1 V1 BUFEN 8 17 VREF VREF BP/ SLEEP 12 13 CS5566 RDY Ready SCLK Serial Clock Input/Output SDO Serial Data Output VL Logic Interface Power VLR Logic Interface Return MCLK Master Clock V2- Negative Voltage 2 V2+ Positive Voltage 2 DCR Digital Core Regulator CONV Convert VLR2 Logic Interface Return ...
Page 27
... SDO is the output pin for the serial output port. Data from this pin will be output at a rate deter- mined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and advances to the next data bit on the rising edges of SCLK. SDO will high impedance state when CS is high. DS806PP1 3/25/08 CS5566 27 ...
Page 28
... CS pin is inactive (high); or two master clock cycles before new data becomes available if the user holds CS low but has not started reading the data from the converter when in SEC mode. 28 3/25/08 CS5566 DS806PP1 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5566 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...
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... ORDERING INFORMATION Model Linearity CS5566-ISZ 0.0005% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5566-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. ...