AD7711ARZ Analog Devices Inc, AD7711ARZ Datasheet
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD7711ARZ
Specifications of AD7711ARZ
Available stocks
Related parts for AD7711ARZ
AD7711ARZ Summary of contents
Page 1
FEATURES Charge-Balancing ADC 24 Bits, No Missing Codes 0.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 1 to 128 1 Differential Input 1 Single-Ended Input Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients RTD Excitation Current ...
Page 2
AD7711–SPECIFICATIONS +2.5 V; REF IN(–) = AGND; MCLK MHz unless otherwise stated. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity @ 25∞ MIN MAX 2, 3 Positive Full-Scale Error ...
Page 3
Parameter 12 V INPUT BIAS Input Voltage Range V Rejection BIAS LOGIC INPUTS Input Current All Inputs except MCLK Input Low Voltage INL V , Input High Voltage INH MCLK IN Only V , Input Low Voltage ...
Page 4
AD7711–SPECIFICATIONS Parameter A, S Versions POWER REQUIREMENTS Power Supply Voltages 16 AV Voltage Voltage – V Voltage 10 Power Supply Currents AV Current Current 4.5 DD ...
Page 5
TIMING CHARACTERISTICS Limit at T MIN Parameter (A, S Versions 400 CLK IN 10 0.4 × CLK IN LO CLK IN 0.4 × CLK IN HI CLK ...
Page 6
AD7711 TIMING CHARACTERISTICS Limit at T Parameter (A, S Versions) External Clocking Mode SCLK CLK ¥ CLK ¥ ...
Page 7
Pin Mnemonic Function 1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes ...
Page 8
AD7711 Pin Mnemonic Function RFS 20 Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external ...
Page 9
CONTROL REGISTER (24 BITS) A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the contents of the control register. The control register ...
Page 10
AD7711 PGA Gain Gain (Default Condition after the Internal Power-On Reset ...
Page 11
Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar input ranges with 2.5 V. These numbers are REF typical and are generated ...
Page 12
AD7711 Figure 2 shows similar information to that outlined in Table I. In these plots, however, the output rms noise is shown for the full range of available cutoffs frequencies. The numbers given in these plots are typical values at ...
Page 13
AD7711’s cali- bration procedure. It also means that the user can verify the calibration is correct by comparing the coefficients after calibra- 2 tion with prestored values in E PROM. The AD7711 can be ...
Page 14
AD7711 First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. On the other hand, analog filtering can remove noise super- imposed on the analog signal ...
Page 15
Table IV. External Series Resistance That Will Not Introduce 16-Bit Gain Error External Capacitance (pF) Gain 0 50 100 500 1 184 kW 45.3 kW 27 88.6 kW 22.1 kW 13 41.4 ...
Page 16
AD7711 IN(+) pin. This REF OUT pin is a single-ended output, refer- enced to AGND, which is capable of providing external load. In applications where REF OUT is connected directly to REF IN(+), REF ...
Page 17
AD7711 into a consistent, known state. A common signal to the AD7711s’ SYNC inputs will synchronize their operation. This would typically be done after each AD7711 has performed its own calibration or has had calibration coefficients loaded to ...
Page 18
AD7711 System calibration can also be used to remove any errors from an antialiasing filter on the analog input. A simple R, C anti- aliasing filter on the front end may introduce a gain error on the analog input voltage, ...
Page 19
Measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. Using the system calibration mode can also minimize offset and ...
Page 20
AD7711 Self-Clocking Mode The AD7711 is configured for its self-clocking mode by tying the MODE pin high. In this mode, the AD7711 provides the serial clock signal used for the transfer of data to and from the AD7711. This self-clocking ...
Page 21
Write Operation Data can be written to either the control register or the calibra- tion registers. In either case, the write operation is not affected by the DRDY line and does not have any effect on the status of DRDY. ...
Page 22
AD7711 Figures 12a and 12b show timing diagrams for reading from the AD7711 in external clocking mode. In Figure 12a, all the data is read from the AD7711 in one operation. In Figure 12b, the data is read from the ...
Page 23
Write Operation Data can be written to either the control register or calibration registers. In either case, the write operation is not affected by the DRDY line and does not have any effect on the status of DRDY. A write ...
Page 24
AD7711 SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE In many applications, the user may not need to write to the on-chip calibration registers. In this case, the serial interface to the AD7711 in external clocking mode can be simplified by connecting ...
Page 25
START CONFIGURE AND INITIALIZE C/ P SERIAL PORT BRING RFS, TFS AND A0 HIGH LOAD DATA FROM ADDRESS TO ACCUMULATOR REVERSE ORDER OF BITS BRING TFS AND A0 LOW WRITE DATA FROM ACCUMULATOR TO SERIAL BUFFER BRING TFS AND A0 ...
Page 26
AD7711 Table VIII. 8XC51 Code for Writing to the AD7711 MOV SCON,#00000000B; Configure 8051 for MODE 0 and Enable Serial Reception MOV IE,#10010000B; Enable Transmit Interrupt MOV IP,#00010000B; Prioritize the Transmit Interrupt Bring TFS High SETB 91H; Bring RFS High ...
Page 27
RTD Configurations One possible 3-wire configuration using the AD7711 is outlined in Figure 20. In the 3-wire configuration, the lead resistances will result in errors if only one current source is used because the 200 mA will flow through ...
Page 28
AD7711 0.005 (0.13) MIN PIN 1 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 Revision History Location 3/04—Data Sheet changed from REV REV. G. Changes to SPECIFICATIONS . . ...