ADC122S051CIMM/NOPB National Semiconductor, ADC122S051CIMM/NOPB Datasheet - Page 16

• Manufacturer Part Number: ADC122S051CIMM/NOPB
• Description: IC ADC 12BIT 2CHAN 500KSPS 8MSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC122S051CIMM/NOPB

• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 500KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5.25V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -1LSB/1.3LSB
• Integral Nonlinearity Error: ±1.1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: MSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S051CIMM; ADC122S051CIMMTR

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the input that is selected for the conversion after the current
one. See Tables 1, 2 and Table 3.
If CS and SCLK go low within the times defined by t
t
DIN may be one clock cycle later than expected. It is, there-
fore, best to strictly observe the minimum t
given in the Timing Specifications.
CLH
, the rising edge of SCLK that begins clocking data in at
Bit 7 (MSB)
DONTC
Bit #:
7 - 6, 2 - 0
3
4
5
ADD2
Symbol:
DONTC
x
x
x
Bit 6
DONTC
ADD0
ADD1
ADD2
ADD1
0
0
1
TABLE 2. Control Register Bit Descriptions
Description
Don't care. The value of these bits do not affect the device.
These three bits determine which input channel will be sampled and converted
in the next track/hold cycle. The mapping between codes and channels is shown
in Table 3.
CSU
ADD2
Bit 5
TABLE 3. Input Channel Selection
and t
TABLE 1. Control Register Bits
ADD0
CLH
0
1
x
CSU
times
ADD1
and
Bit 4
Not allowed. The output signal at the D
16
is indeterminate if ADD1 is high.
There are no power-up delays or dummy conversions re-
quired with the ADC122S051. The ADC is able to sample and
convert an input to full conversion immediately following pow-
er up. The first conversion result after power-up will be that of
IN1.
ADD0
Bit 3
Input Channel
IN1 (Default)
IN2
DONTC
Bit 2
OUT
DONTC
Bit 1
pin
DONTC
Bit 0