ADC128S102CIMT/NOPB National Semiconductor, ADC128S102CIMT/NOPB Datasheet - Page 15

• Manufacturer Part Number: ADC128S102CIMT/NOPB
• Description: ADC 12BIT 8CH 0.5-1MSPS 16TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC128S102CIMT/NOPB

• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 10.7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• For Use With: ADC128S102EVAL - BOARD EVALUATION FOR ADC128S102
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC128S102CIMT; *ADC128S102CIMT/NOPB; ADC128S102CIMT

condition, the ADC automatically enters track mode and the
falling edge of CS is seen as the first falling edge of SCLK. In
the third condition, CS and SCLK go low simultaneously and
the ADC enters track mode. While there is no timing restriction
with respect to the rising edges of CS and SCLK, see
3
CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next
input for conversion is clocked into a control register through
1.3 ADC128S102 TRANSFER FUNCTION
The output format of the ADC128S102 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC128S102 is V
The ideal transfer characteristic is shown in
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of V
Other code transitions occur at steps of one LSB.
for setup and hold time requirements for the falling edge of
ADD2
Bit 7 (MSB)
DONTC
0
0
0
0
1
1
1
1
Bit #:
7, 6, 2, 1, 0
5
4
3
FIGURE 6. Ideal Transfer Characteristic
TABLE 3. Input Channel Selection
ADD1
0
0
1
1
0
0
1
1
Symbol:
DONTC
ADD2
ADD1
ADD0
DONTC
Bit 6
ADD0
0
1
0
1
0
1
0
1
TABLE 2. Control Register Bit Descriptions
Input Channel
Description
Don't care. The values of these bits do not affect the device.
These three bits determine which input channel will be sampled and converted
at the next conversion cycle. The mapping between codes and channels is
shown in
IN0 (Default)
ADD2
Bit 5
Figure
IN1
IN2
IN3
IN4
IN5
IN6
IN7
TABLE 1. Control Register Bits
Table
A
A
20136111
/ 8192.
/ 4096.
6. The
Figure
ADD1
Bit 4
3.
15
the DIN pin on the first 8 rising edges of SCLK after the fall of
CS. See Tables 1, 2, 3.
There is no need to incorporate a power-up delay or dummy
conversions as the ADC128S102 is able to acquire the input
signal to full resolution in the first conversion immediately fol-
lowing power-up. The first conversion result after power-up
will be that of IN0.
1.4 ANALOG INPUTS
An equivalent circuit for one of the ADC128S102's input chan-
nels is shown in
protection for the analog inputs. The operating range for the
analog inputs is 0 V to V
the ESD diodes to conduct and result in erratic operation.
The capacitor C1 in
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch and is
typically 500 ohms. Capacitor C2 is the ADC128S102 sam-
pling capacitor, and is typically 30 pF. The ADC128S102 will
deliver best performance when driven by a low-impedance
source (less than 100 ohms). This is especially important
when using the ADC128S102 to sample dynamic signals. Al-
so important when sampling dynamic signals is a band-pass
or low-pass filter which reduces harmonics and noise in the
input. These filters are often referred to as anti-aliasing filters.
1.5 DIGITAL INPUTS AND OUTPUTS
The ADC128S102's digital inputs (SCLK, CS, and DIN) have
an operating range of 0 V to V
up and may be asserted before the digital supply (V
any risk. The digital output (DOUT) operating range is con-
trolled by V
the output low voltage is 0.4V (max).
ADD0
Bit 3
D
FIGURE 7. Equivalent Input Circuit
. The output high voltage is V
DONTC
Bit 2
Figure
Figure 7
A
7. Diodes D1 and D2 provide ESD
. Going beyond this range will cause
has a typical value of 3 pF and
A
. They are not prone to latch-
DONTC
Bit 1
D
- 0.5V (min) while
20136114
DONTC
www.national.com
Bit 0
D
) without