KAD5514P-25Q48 Intersil, KAD5514P-25Q48 Datasheet - Page 21

• Manufacturer Part Number: KAD5514P-25Q48
• Description: IC ADC 14BIT 250MSPS SGL 48-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5514P-25Q48

• Number Of Bits: 14
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 463mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• For Use With: KDC5514-Q48EVAL - DAUGHTER CARD FOR KAD5514KDC5514EVALZ - DAUGHTER CARD FOR KAD5514
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power
saving modes are available: Nap, and Sleep. Nap mode
reduces power dissipation to less than 163mW and recovers
to normal operation in approximately 1µs. Sleep mode
reduces power dissipation to less than 6mW but requires
approximately 1ms to recover from a sleep command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during
sleep, requiring a user to wait 150µs max after CSB is
asserted (brought low) prior to writing ‘001x’ to SPI
Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150us
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150µs CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation
increases by ~ 15mW in this case. The 1ms wake-up time
after the write of a ‘001x’ to register 25 still applies. It is
generally recommended to keep CSB high in sleep mode to
avoid any unintentional SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep, and CSB should be high. Recovery time from Nap
mode will increase if the clock is stopped, since the internal
DLL can take up to 52µs to regain lock at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
NAPSLP PIN
AVSS
AVDD
Float
TABLE 3. NAPSLP PIN SETTINGS
21
Normal
MODE
Sleep
Nap
KAD5514P
The power-down mode can also be controlled through the
SPI port, which overrides the NAPSLP pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
page 22. This is an indexed function when controlled from
the SPI, but a global function when driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 4.
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in the “Serial Peripheral Interface” on page 22.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF
(all ones). Two’s complement coding simply complements
the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows
this operation.
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 34.
GRAY CODE
FIGURE 33. BINARY TO GRAY CODE CONVERSION
BINARY
OUTFMT PIN
AVDD
AVSS
Float
TABLE 4. OUTFMT PIN SETTINGS
13
13
12
12
11
11
Two’s Complement
Offset Binary
• • • •
• • • •
• • • •
Gray Code
MODE
September 10, 2009
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