LTC2442IG#PBF Linear Technology, LTC2442IG#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC2442IG#PBF
• Description: IC ADC 24BIT 4CH 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2442IG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC2442
the fi rst falling edge of SCK. The fi nal data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the SEL
tained within the –0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Serial Interface Pins
The LTC2442 transmits the conversion result and receives
the start of conversion command through a synchronous
3- or 4-wire interface. During the conversion and sleep
states, this interface can be used to access the converter
status and during the data output state it is used to read
the conversion result and program the speed, resolution
and input channel.
12
Table 2. LTC2442 Output Data Format
Differential Input Voltage
V
V
0.5 • V
0.25 • V
0.25 • V
0
–1LSB
–0.25 • V
–0.25 • V
–0.5 • V
V
*The differential input voltage V
IN
IN
IN
*
* ≥ 0.5 • V
* < –0.5 • V
REF
REF
REF
REF
REF
REF
** –1LSB
**
** –1LSB
**
**
** –1LSB
REF
REF
**
REF
**
. For differential input voltages greater
U
IN
Bit 31
U
EOC
= SEL
IN
0
0
0
0
0
0
0
0
0
0
CC
from –FS = –0.5 • V
+ 0.3V) absolute maximum
+
– SEL
+
and SEL
W
Bit 30
DMY
–
. **The differential reference voltage V
0
0
0
0
0
0
0
0
0
0
–
pins is main-
Bit 29
U
SIG
1
1
1
1
1
0
0
0
0
0
REF
to
Bit 28
MSB
1
0
0
0
0
1
1
1
1
0
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 1) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2442 creates its own serial clock. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected
by tying EXT (Pin 3) LOW for external SCK and HIGH for
internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 36), provides the
result of the last conversion as a serial bit stream (MSB
fi rst) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 35) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the fi rst
rising edge of SCK occurs while CS = LOW.
Bit 27
REF
0
1
1
0
0
1
1
0
0
1
= REF
+
– REF
Bit 26
0
1
0
1
1
0
1
0
1
0
–
.
Bit 25
0
1
0
1
0
1
0
1
0
1
...
...
...
...
...
...
...
...
...
...
...
Bit 0
0
1
0
1
0
1
0
1
0
1
2442f