CS5340-DZZ Cirrus Logic Inc, CS5340-DZZ Datasheet - Page 16

• Manufacturer Part Number: CS5340-DZZ
• Description: IC ADC AUD 101DB 200KHZ 16-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5340-DZZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 3.1V To 5.25V
• Supply Current: 21mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1544 - BOARD EVAL FOR CS5340 STEREO ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1686

16
4.2.1
4.2.2
MCLK
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed
Modes, respectively). Please refer to
Figure
18.
÷ 1
÷ 2
Auto-Select
Figure 18. CS5340 Master Mode Clocking
0
1
Confidential Draft
Table
3/11/08
for supported sample rate ranges.
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
Double
Speed
Speed
Speed
Single
Speed
Speed
Speed
Single
Quad
Quad
M1
00
01
10
00
01
10
M0
SCLK Output
LRCK Output
(Equal to Fs)
CS5340
DS601F2