AD7713ARZ Analog Devices Inc, AD7713ARZ Datasheet
AD7713ARZ
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AD7713ARZ Summary of contents
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FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity 3-Channel Programmable Gain Front End Gains from 1 to 128 2 Differential Inputs 1 Single-Ended High Voltage Input Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients ...
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AD7713–SPECIFICATIONS MCLK MHz, unless otherwise noted. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity Positive Full-Scale Error 5 Full-Scale Drift 2, 4 Unipolar Offset Error 5 Unipolar Offset Drift ...
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Parameter REFERENCE INPUT REF IN(+) – REF IN(–) Voltage Input Sampling Rate Normal-Mode 50 Hz Rejection 6 Normal-Mode 60 Hz Rejection Common-Mode Rejection (CMR) 6 Common-Mode 50 Hz Rejection 6 Common-Mode 60 Hz Rejection 10 Common-Mode Voltage ...
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AD7713 Parameter AIN3 Positive Full-Scale Calibration Limit 15 Offset Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltages 16 AV Voltage Voltage DD Power Supply Currents AV Current DD DV Current DD 18 Power Supply Rejection 19 ...
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TIMING CHARACTERISTICS Limit at T Parameter (A, S Versions 400 CLK 0.4 t CLK IN LO CLK IN t 0.4 t CLK IN HI CLK ...
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AD7713 ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted AGND . . . . . . . . . . . . . . . . . . . . . . . –0 ...
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Pin No. Mnemonic Function 1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK ...
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AD7713 Pin No. Mnemonic Function Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as 16 RTD2 the excitation current for RTDs. This current can be turned on or off via ...
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CONTROL REGISTER (24 BITS) A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the contents of the control register. The control register ...
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AD7713 PGA Gain Gain (Default Condition after the Internal Power-On Reset ...
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Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar input ranges with 2.5 V. These numbers are REF typical and are generated ...
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AD7713 Figures 2a and 2b gives similar information to that outlined in Table I. In this plot, the output rms noise is shown for the full range of available cutoff frequencies rather than for some typical cutoff frequencies as in ...
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The AD7713 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the device’s calibra- tion coefficients and also to write its own calibration coefficients 2 to the part from prestored values in E PROM. This ...
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AD7713 DIGITAL FILTERING The AD7713’s digital filter behaves like a similar analog filter, with a few minor differences. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot ...
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In any case, the error introduced due to longer charging times is a gain error that can be removed using the system calibration capabilities of the AD7713 provided that the resultant span is within the span limits of the system ...
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AD7713 look like the AIN1 analog input (see Figure 7). In this case kΩ typ and C varies with gain. The input sample rate is INT f /256 and does not vary with gain. For gains of ...
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MD2, MD1, and MD0 bits of the control register. In this cali- bration mode, the shorted inputs node is switched in to the modulator first and a conversion ...
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AD7713 The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. This offset range is limited by the requirement that the positive full-scale calibration limit is ≤ 1.05 V /GAIN for ...
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DRDY (O) A0 (I) RFS (I) SCLK (O) SDATA (O) Figure 10. Self-Clocking Mode, Output Data Read Operation A0 (I) TFS (I) SCLK (O) SDATA (I) Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation word in the output register. If ...
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AD7713 DRDY (O) A0 (I) RFS (I) SCLK (I) SDATA (O) Figure 12a. External Clocking Mode, Output Data Read Operation DRDY (O) A0 (I) RFS (I) SCLK (I) SDATA (O) Figure 12b. External Clocking Mode, Output Data Read ( RFS ...
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A0 (I) TFS (I) SCLK (I) SDATA (I) Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation A0 (I) TFS (I) SCLK (I) SDATA (I) Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation ( TFS Returns High During Write ...
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AD7713 MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7713’s flexible serial interface allows easy interface to most microcomputers and microprocessors. Figure 15 shows a flowchart diagram for a typical programming sequence for read- ing data from the AD7713 to a microcomputer, while Figure 16 ...
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Table V shows some typical 8XC51 code used for a single 24-bit read from the output register of the AD7713. Table V shows some typical code for a single write operation to the control register of the AD7713. The 8XC51 ...
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AD7713 PC0 PC1 PC2 68HC11 PC3 SCK MISO MOSI Figure 18. AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations Figure 19 shows a 4-wire RTD application where the RTD transducer is interfaced directly to the ...
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OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE AD7710 FEATURES Charge Balancing 24 Bits No Missing Codes 0.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 1 to 128 Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients ...
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AD7713 AD7712 FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity High Level and Low Level Analog Input Channels Programmable Gain for Both Inputs Gains from 1 to 128 Differential Input for Low Level Channel Low-Pass Filter with ...
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MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 REV. D OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches ...
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AD7713 Revision History Location 3/04—Data Sheet changed from REV REV. D. Updated layout . . . . . . . . . . . . . . . . . . . . . . . . . ...