AD9269BCPZ-40 Analog Devices Inc, AD9269BCPZ-40 Datasheet
AD9269BCPZ-40
Specifications of AD9269BCPZ-40
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AD9269BCPZ-40 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply Integrated quadrature error correction (QEC) SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc ...
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AD9269 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 6 Digital Specifications ...
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GENERAL DESCRIPTION The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic ...
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AD9269 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. AD9269-20/AD9269-40 Parameter Temp Min RESOLUTION ...
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AD9269-20/AD9269-40 Parameter Temp Min POWER CONSUMPTION DC Input Full 2 Full Sine Wave Input (DRVDD = 1 Full Sine Wave Input (DRVDD = 3 Standby Power Full Power-Down Power Full 1 Measured with a 1.0 V ...
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AD9269 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR) f ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic ...
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AD9269 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock ...
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TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the ...
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AD9269 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D0B (LSB) DRVDD NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Table 8. Pin Function Descriptions Pin No. Mnemonic Description ...
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AD9269 Pin No. Mnemonic Description 49, 50, 53, 54, AVDD 1.8 V Analog Supply Pins. 59, 60, 63, 64 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9269-80 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 80MSPS 9.7MHz @ –1dBFS –20 SNR ...
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AD9269 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 SFDR (dBc SNR (dBFS ...
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AD9269-65 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 65MSPS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) ...
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AD9269 AD9269-40 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS –20 SNR = 76.9dB ...
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AD9269-20 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 20MSPS 9.7MHz @ –1dBFS –20 SNR = 76.9dB (77.9dBFS) ...
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AD9269 EQUIVALENT CIRCUITS AVDD VIN±x Figure 29. Equivalent Analog Input Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ Figure 30. Equivalent SDIO/DCS Input Circuit DRVDD 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input ...
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THEORY OF OPERATION The AD9269 dual-channel ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog ...
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AD9269 Input Common Mode The analog inputs of the AD9269 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but ...
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In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values ...
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AD9269 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 47 shows the typical drift characteristics of the internal reference in 1.0 ...
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If a low jitter clock source is not available, another option couple a differential PECL signal to the sample clock input pins, as shown in Figure 51. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 excellent jitter performance. 0.1µF CLOCK INPUT AD951x ...
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AD9269 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low fre- quency SNR (SNR ) at a given input frequency (f LF jitter (t ) can ...
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The AD9269 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 1 mW. During power-down, the output drivers are placed in a high impedance state. ...
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AD9269 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9269 includes a built-in test feature that is designed to enable verification of the integrity of each channel as well as to facilitate board-level debugging. A built-in self-test (BIST) feature that verifies ...
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CHANNEL/CHIP SYNCHRONIZATION The AD9269 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or ...
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AD9269 DC AND QUADRATURE ERROR CORRECTION (QEC) In direct conversion or other quadrature systems, mismatches between the real (I) and imaginary (Q) signal paths cause fre- quencies in the positive spectrum to image into the negative spectrum, and vice versa. ...
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SERIAL PORT INTERFACE (SPI) The AD9269 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a struc- tured register space provided inside the ADC. The SPI provides added flexibility and customization, depending ...
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AD9269 The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 17) contains eight bit locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); ...
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AD9269 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr. Register (MSB) (Hex) Name Bit 7 Chip configuration registers 0x00 SPI port 0 ...
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Addr. Register (MSB) (Hex) Name Bit 7 0x0D Test mode (local) User test mode (local single 01 = alternate 10 = single once 11 = alternate once 0x0E BIST enable Open 0x10 Offset adjust 8-bit device offset adjustment ...
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AD9269 Addr. Register (MSB) (Hex) Name Bit 7 0x2A Features Open 0x2E Output assign Open Digital feature control 0x100 Sync control Open (global) 0x101 USR2 Enable OEB (Pin 47) (local) 0x110 QEC Control 0 Open 0x111 QEC Control 1 0x112 ...
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Bit 1—Open Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. ...
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AD9269 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9269 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements required for certain pins. ...
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... AD9269BCPZ-80 –40°C to +85°C 2 AD9269BCPZRL7-80 –40°C to +85°C AD9269BCPZ-65 2 –40°C to +85°C 2 AD9269BCPZRL7-65 –40°C to +85°C AD9269BCPZ-40 2 –40°C to +85°C 2 AD9269BCPZRL7-40 –40°C to +85°C 2 AD9269BCPZ-20 –40°C to +85°C 2 AD9269BCPZRL7-20 –40°C to +85°C AD9269-80EBZ ...
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AD9269 NOTES Rev Page ...
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NOTES Rev Page AD9269 ...
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AD9269 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08538-0-1/10(0) Rev Page ...