MAX1421ECM+D Maxim Integrated Products, MAX1421ECM+D Datasheet - Page 11

• Manufacturer Part Number: MAX1421ECM+D
• Description: IC ADC 12BIT 40MSPS 48LQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1421ECM+D

• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 214mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1421 provides three modes of reference oper-
ation:
•
•
•
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22µF, in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
The MAX1421’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
R
R
AV
DD
______________________________________________________________________________________
Clock Inputs (CLK,
12-Bit, 40Msps, 3.3V, Low-Power ADC
AV
AV
R
R
2
4
DD
DD
C C L L K K )
MAX4284
MAX4284
AV
AV
2
4
50Ω
DD
DD
with Internal Reference
+1V
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
where f
t
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AV
specifications for high and low periods, as stated in the
Electrical Characteristics.
AJ
R
R
R
R
0.22µF
50Ω
50Ω
0.22µF
0.22µF
is the aperture jitter.
AGND
IN
S
NR
represents the analog input frequency and
dB
1nF
1nF
1nF
=
20
DD
REFIN
REFN
REFP
CML
×
( )
/ 2. Clock inputs must meet the
log
(
(
AV
AV
AV
2
2
MAX1421
2
DD
DD
DD
10
+ 1V
+ 1V



)
)
2
π ƒ
×
IN
1
×
t
AJ



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