LTC1860CS8 Linear Technology, LTC1860CS8 Datasheet - Page 11

• Manufacturer Part Number: LTC1860CS8
• Description: IC A/D CONV 1CH 12BIT 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1860CS8

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
LTC1860 OPERATION
Operating Sequence
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to t
fi nished. If CONV is left high after this time, the LTC1860
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
•
•
•
CONV
SDO
SCK
Figure 2. LTC1860 Transfer Curve
t
CONV
*V
IN
= IN
CONV
+
– IN
, the conversion is
–
Hi-Z
Figure 1. LTC1860 Operating Sequence
SLEEP MODE
1860 F02
V
IN
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
and “IN
IN
equals V
“IN
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and V
span will result on “IN
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defi nes the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from V
*
–
–
equals zero. Full scale occurs when IN
” inputs are sampled at the same time, so common
V
IN
–
= 0V TO V
REF
” inputs. A zero code will occur when IN
B11 B10
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
Figure 3. LTC1860 with Rail-to-Rail Input Span
1
minus 1LSB. See Figure 2. Both the “IN
2
CC
B9
CC
t
suCONV
3
1
2
3
4
B8
to 1V.
REF
4
V
IN
IN
GND
LTC1860/LTC1861
REF
+
–
B7
LTC1860
5
+
is tied to V
” as shown in Figure 3.
B6
t
6
CONV
SMPL
SDO
SCK
V
B5
1 F
CC
7
B4
8
1860 F03
8
7
6
5
B3
9
B2
CC
10
V
CC
, a rail-to-rail input
B1
11
B0*
12
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Hi-Z
+
minus IN
+
11
minus
+
” and
18601fa
+
–
”
–
”