LTC1860CS8 Linear Technology, LTC1860CS8 Datasheet - Page 12

• Manufacturer Part Number: LTC1860CS8
• Description: IC A/D CONV 1CH 12BIT 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1860CS8

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
LTC1860/LTC1861
LTC1861 OPERATION
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to t
fi nished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems.
The data is transmitted and received simultaneously (full
duplex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefi nitely. See Figure 4.
12
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
•
•
•
CONV
SDO
SCK
SDI
Figure 5. LTC1861 Transfer Curve
*V
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
IN
= (SELECTED “+” CHANNEL) –
t
CONV
CONV
, the conversion is
DON’T CARE
Hi-Z
Figure 4. LTC1861 Operating Sequence
SLEEP MODE
1860 F05
V
IN
Analog Inputs
The two bits of the input word (SDI) assign the MUX
confi guration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND (or AGND). A zero code will occur when
the “+” input minus the “–” input equals zero. Full scale
occurs when the “+” input minus the “–” input equals
V
inputs are sampled at the same time so common mode
noise is rejected. The input span in the SO-8 package is
fi xed at V
is grounded, a rail-to-rail input span will result on the
“+” input.
*
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
REF
SINGLE-ENDED
DIFFERENTIAL
MUX MODE
MUX MODE
minus 1LSB. See Figure 5. Both the “+” and “–”
S/D O/S
B11 B10
REF
1
2
= V
B9
Table 1. Multiplexer Channel Selection
3
SGL/DIFF
CC
B8
4
MUX ADDRESS
. If the “–” input in differential mode
1
1
0
0
B7
5
B6
6
DON’T CARE
t
B5
ODD/SIGN
SMPL
7
B4
8
0
1
0
1
B3
9
B2
10
B1
11
CHANNEL #
0
+
+
–
B0*
12
1860 F04
Hi-Z
1
+
–
+
GND
186465 TBL1
–
–
18601fa