LTC2439-1CGN#TRPBF Linear Technology, LTC2439-1CGN#TRPBF Datasheet - Page 17

• Manufacturer Part Number: LTC2439-1CGN#TRPBF
• Description: IC ADC 16BIT 16CH MCRPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2439-1CGN#TRPBF

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(INTERNAL)
APPLICATIO S I FOR ATIO
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the conversion is complete.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
SDO
SCK
SDI
CS
CONVERSION
Hi-Z
DON’T CARE
SLEEP
TEST EOC
U
SLEEP
Hi-Z
<t
EOCtest
U
(1)
BIT 18
EOC
BIT 17
“O”
(0)
W
Figure 9. Internal Serial Clock, Single Cycle Operation
BIT 16
SIG
EN
0.1V TO V
REFERENCE
BIT 15
U
MSB
ANALOG
INPUTS
VOLTAGE
SGL
1µF
2.7V TO 5.5V
CC
BIT 14
•
•
•
•
•
•
11
12
21
28
10
ODD/
SIGN
9
1
8
DATA OUTPUT
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
LTC2439-1
•
•
•
•
•
•
+
–
BIT 13
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
after the falling edge of CS (if EOC = 0) or t
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
oscillator (F
external oscillator of frequency f
3.6/f
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 19th rising edge. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 19th rising edge of
SCK. After the 19th rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
A2
SDO
GND
SCK
SDI
CS
F
O
17
15
EOSC
20
18
19
BIT 12
16
A1
. If CS is pulled HIGH before time t
4-WIRE
SPI INTERFACE
BIT 11
O
EOCtest
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
A0
= logic LOW or HIGH). If F
50Hz/60Hz REJECTION
is 23µs if the device is using its internal
DON’T CARE
BIT 6
V
CC
10k
EOCtest
EOSC
LTC2439-1
, then t
BIT 0
O
LSB
, the first rising
EOCtest
is driven by an
EOCtest
CONVERSION
after EOC
EOCtest
Hi-Z
17
EOCtest
TEST EOC
, the
24391fa
24391 F08
Hi-Z
is