LTC2420CS8 Linear Technology, LTC2420CS8 Datasheet - Page 20

• Manufacturer Part Number: LTC2420CS8
• Description: IC ADC 20BIT MICRPWR W/OSC 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC2420CS8

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q1156784

APPLICATIO S I FOR ATIO
LTC2420
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground (Pin 4),
simplifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
(INTERNAL)
20
SDO
SCK
CS
CONVERSION
U
BIT 23
U
EOC
CC
exceeds 2.2V. An internal
SLEEP
BIT 22
Figure 11. Internal Serial Clock, Continuous Operation
W
–0.12V
BIT 21
SIG
REF
TO 1.12V
0.1V TO V
U
BIT 20
EXR
1 F
2.7V TO 5.5V
V
REF
V
REF
CC
IN
BIT 19
MSB
V
V
V
GND
CC
REF
IN
LTC2420
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 24th rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 24th
rising edge of SCK. After the 24th rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
DATA OUTPUT
BIT 18
SDO
SCK
CS
F
O
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 4
LSB
BIT 0
20
CONVERSION
2420 F11