LTC2420IS8 Linear Technology, LTC2420IS8 Datasheet - Page 12

• Manufacturer Part Number: LTC2420IS8
• Description: IC ADC 20BIT MICROPOWER 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC2420IS8

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2420
fault current, a resistor of up to 25k may be added in series
with the V
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
therefore, the resistor should be located as close as
practical to the V
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
has a very strong temperature dependency.
Output Data Format
The LTC2420 serial output data stream is 24 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 20 bits are
the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW. The sign bit changes state during the zero code.
12
IN
pin without affecting the performance of the
SDO
SCK
CS
IN
IN
is >0, this bit is HIGH. If V
pin. The effect of the series resistance
U
Hi-Z
SLEEP
U
BIT 23
EOC
IN
1
pin as low as possible;
BIT 22
“0”
W
REF
2
= 5V. This error
BIT 21
IN
SIG
Figure 4. Output Data Timing
is <0, this
U
3
BIT 20
EXT
4
DATA OUTPUT
BIT 19
MSB
Bit 20 (fourth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0 V
normal input range, V
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Input Range
V
0 < V
V
V
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
IN
IN
IN
5
> V
= 0
< 0
IN
+
IN
REF
/0
V
–
REF
V
REF
19
, this bit is LOW. If the input is outside the
BIT 4
Bit 23
EOC
20
0
0
0
0
IN
> V
LSB
BIT 0
REF
20
24
Bit 22
DMY
or V
0
0
0
0
CONVERSION
IN
< 0, this bit is HIGH.
Bit 21
2420 F04
SIG
1/0
1
1
0
Bit 20
EXR
1
0
0
1