LTC2220CUP-1#TRPBF Linear Technology, LTC2220CUP-1#TRPBF Datasheet - Page 20
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LTC2220CUP-1#TRPBF
Manufacturer Part Number
LTC2220CUP-1#TRPBF
Description
IC ADC 12BIT 185MSPS 64-QFN
Manufacturer
Linear Technology
Datasheet
1.LTC2220CUP-1TRPBF.pdf
(28 pages)
Specifications of LTC2220CUP-1#TRPBF
Number Of Bits
12
Sampling Rate (per Second)
185M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
1.18W
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-WFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
20
LTC2220-1
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2220-1 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
APPLICATIO S I FOR ATIO
+
/OF
–
LTC2220-1
or CLKOUT
DD
Figure 13b. Digital Output in LVDS Mode
–
+
D
D
voltages will also help reduce interference
1.25V
+
to OUT
U
+
10k
/CLKOUT
OV
DD
10k
OGND
U
3.5mA
–
or vice versa which creates a
–
). To minimize noise the
22201 F13b
D
D
W
OUT
OUT
100Ω
+
–
RECEIVER
U
LVDS
Table 3. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT
edge of CLKOUT
Data Format
The LTC2220-1 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
DD
DD
DD
DD
DD
or 2/3V
selects offset binary output format. Connecting
+
/CLKOUT
DD
2’s Complement
2’s Complement
DD
Output Format
Offset Binary
Offset Binary
+
/CLKOUT
or V
–
logic values. Table 3 shows the logic
rises and can be latched on the falling
DD
selects 2’s complement output
–
.
+
/OF
Cycle Stablizer
–
Clock Duty
pins indicates an
+
Off
Off
On
On
input available
2220_1fa