LTC2220IUP-1#TRPBF Linear Technology, LTC2220IUP-1#TRPBF Datasheet - Page 16

• Manufacturer Part Number: LTC2220IUP-1#TRPBF
• Description: IC ADC 12BIT 185MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2220IUP-1#TRPBF

• Number Of Bits: 12
• Sampling Rate (per Second): 185M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.18W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
16
LTC2220-1
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The V
60) may be used to provide the common mode bias level.
V
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2220-1 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the sample-
and-hold circuit will connect the 1.6pF sampling capacitor
to the input pin and start the sampling period. The sam-
pling period ends when ENC rises, holding the sampled
input on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2F
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2220-1 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
CM
can be tied directly to the center tap of a transformer
U
U
CM
CM
pin must be bypassed to
W
, setting the ADC input
ENCODE
CM
output pin (Pin
); however,
U
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth
of most op amps will limit the SFDR at high input frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
cies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
ANALOG
Figure 4. Differential Drive with an Amplifier
INPUT
AMPLIFIER = LTC6600-20, LT1993, ETC.
ANALOG
ANALOG
INPUT
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
INPUT
0.1µF
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 5. Single-Ended Drive
DIFFERENTIAL
HIGH SPEED
AMPLIFIER
0.1µF
+
CM
–
1:1
T1
1k
+
–
25Ω
25Ω
25Ω
25Ω
1k
3pF
0.1µF
25Ω
25Ω
25Ω
25Ω
0.1µF
2.2µF
12pF
12pF
2.2µF
3pF
V
A
A
A
A
2.2µF
12pF
CM
IN
IN
IN
IN
V
V
+
+
–
–
A
A
A
A
A
A
A
A
CM
CM
IN
IN
IN
IN
IN
IN
IN
IN
+
+
–
–
+
+
–
–
LTC2220-1
LTC2220-1
LTC2220-1
22201 F05
22201 F04
22201 F03
2220_1fa