CS5510-ASZ Cirrus Logic Inc, CS5510-ASZ Datasheet - Page 7

• Manufacturer Part Number: CS5510-ASZ
• Description: IC ADC 16BIT EXTERNAL OSC 8-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5510-ASZ

• Number Of Converters: 1
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Number Of Bits: 16
• Sampling Rate (per Second): 326
• Data Interface: Serial
• Power Dissipation (max): 1.9mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 16 SPs to 326 SPs
• Resolution: 16 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: 250 mV to 5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SWITCHING CHARACTERISTICS - CS5510/12
(T
Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or
DS337F4
Master Clock Timing
Master Clock Frequency (CS5510)
Master Clock Frequency (CS5512)
Master Clock Duty Cycle
Rise Times
Fall Times
Serial Port Timing
Serial Clock Frequency (CS5510)
Serial Clock Frequency (CS5512)
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Serial Clock
SDO Read Timing
CS
SCLK Falling to New Data Bit
CS
CS
A
= 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C
to Data Valid
Rising to SDO Hi-Z
Falling to SCLK Rising
21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as
200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.
well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t
the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t
longer.
Parameter
Pulse Width High
Pulse Width Low
(Note 20) SCLK
(Note 20) SCLK
(Note 21)
(Note 21)
(Note 22) SCLK
(Note 22) SCLK
(Note 22)
(Note 22) t
SCLK
SCLK
SDO
SDO
CSB
CSB
Symbol
WAKE
t
t
t
SLP
t
rise
fall
t
t
t
t
t
11
1
2
3
4
5
L
Min
200
200
= 50 pF)
10
10
40
10
10
10
2
2
-
-
-
-
-
-
-
-
-
CS5510/11/12/13
32.768
32.768
32.768
32.768
Typ
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
2000
Max
130
200
130
200
150
150
150
1.0
1.0
60
10
10
60
60
SLP
-
-
-
-
or longer,
WAKE
Unit
kHz
kHz
kHz
kHz
µs
µs
ns
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
%
or
7