AD9280ARS Analog Devices Inc, AD9280ARS Datasheet - Page 18

• Manufacturer Part Number: AD9280ARS
• Description: IC ADC CMOS 8BIT 32MSPS 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9280ARS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 8
• Sampling Rate (per Second): 32M
• Data Interface: Parallel
• Number Of Converters: 9
• Power Dissipation (max): 110mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Number Of Elements: 1
• Resolution: 8Bit
• Architecture: Pipelined
• Sample Rate: 32MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 3V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 110mW
• Differential Linearity Error: ±1LSB
• Integral Nonlinearity Error: ±1.5LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• For Use With: AD9280-EB - BOARD EVAL FOR AD9280
• Lead Free Status / RoHS Status: Not Compliant

AD9280
THREE-STATE
REFSENSE
+3–5A
CLAMPIN
DUTCLK
CLAMP
AVDD
REFTS
REFBF
REFBS
REFTF
NOTE:
THE AD9280 IS EXERCISED IN
AN AD9200 EVALUATION BOARD
MODE
STBY
VREF
J7
AD1580
5.49k
AIN
R7
10/10V
D1
C16
0.1 F
GND
C33
R53
49.9
+
TP14
15
16
17
18
19
20
21
22
23
24
25
26
27
C17
10/10V
CLK
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
REFTF
MODE
REFBF
REFBS
VREF
AIN
AVDD
AVSS
10k
XXXX
ADJ.
AD9280
28
1
JP17
JP18
R8
JP5
U1
DRVSS
DRVDD
CW
R9
1.5k
2
XXXX
ADJ.
14
OTR
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
5k
R10
NC
NC
R37
1k
R38
1k
R39
1k
CW
C18
10/10V
WHITE
13
10
11
12
3
4
5
6
7
8
9
C8
10/10V
C19
0.1 F
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
3
TP19
OTR
AD822
15k
DRVDD
R11
10k
R12
+3–5A
U2
TP11
C9
10/10V
DRVDD
8
4
DRVDD
Figure 39a. Evaluation Board Schematic
DRVDD
0.1 F
3
CLK
2
1
C7
AD822
0.1 F
GND
C40
U3
+3–5A
B
B
GND
C41
0.1 F
11k
R13
8
4
1
3
1
3
0.1 F
C10
A
A
S3 2
S4
1
GND
D5
D6
D7
D8
D9
D0
D1
D2
D3
D4
GND
2
16
15
21
20
19
18
17
14
24
23
22
13
19
20
21
18
17
16
15
14
24
23
22
13
74LVXC4245WM
5
6
74LVXC4245WM
B
B
B
B
B
B
B
B
VCCB VCCA
NC1
OE
GD1 U4 GD3
B
B
B
B
B
B
B
B
VCCB VCCA
NC1
OE
GD1 U5 GD3
–18–
6
5
AD822
U2
U4
U4
U4
U4
U4
U4
U4
U4
U5
U5
U5
U5
U5
U5
U5
U5
AD822
U3
GND
GD2
GD2
T/R
T/R
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3
5
4
3
6
7
8
9
10
1
11
12
7
8
9
3
4
5
6
10
1
2
11
12
2
7
+3–5A
JP20
2
0.1 F
1k
R15
C11
GND
0.1 F
1k
C29
R16
GND
1
3
C20
0.1 F
C21
0.1 F
CM
2
R17
316
+3–5D
R18
316k
GND
JP21
1
C43
0.1 F
+3–5D
GND
R19
178
R20
178
B
C42
0.1 F
Q2
2N3904
Q1
2N3906
1
3
+3–5D
A
S2
0.626V TO 4.8V
2
C12
0.1 F
C14
0.1 F
2
4
2
7
5
6
RN1
22
RN1
22
RN1
22
RN2
22
RN2
22
RN2
22
10
12
11
13
15
15
1
4
1
6
5
3
C13
10/10V
C15
10/10V
RN1
22
RN1
22
RN2
22
RN2
22
RN2
22
RN1
22
CLK
13
12
16
11
16
14
WHITE
TP16
CLK_OUT
TP17
13
11
19
17
15
33
23
21
9
7
5
1
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
EXTT
EXTB
CLAMP
THREE-STATE
STBY
NC
NC
NC
REV. E
27
25
10
12
14
16
18
20
22
24
26
39
28
29
30
31
32
34
35
36
37
38
40
3
2
4
6
8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8