AD7450ABRMZ Analog Devices Inc, AD7450ABRMZ Datasheet - Page 7

• Manufacturer Part Number: AD7450ABRMZ
• Description: IC ADC 12BIT DIFF IN 1MSPS 8MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7450ABRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 9.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 1.95mA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7450CBZ - BOARD EVALUATION FOR AD7450
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
1.6 V. See Figure 2, Figure 3, and the Serial Interface section.
Table 3. V
V
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Common-mode voltage.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
t
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
See Power-Up Time section.
3
3
4
8
REF
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
2
= 2.5 V; V
5
DD
= 2.7 V to 3.6 V, f
CM
SDATA
SDATA
Limit at T
10
18
16 × t
888
60
10
10
20
40
0.4 t
0.4 t
10
10
35
1
SCLK
SCLK
1
CS
CS
= V
SCLK
SCLK
SCLK
REF
t
t
t
t
2
3
2
3
MIN
; T
, T
A
0
0
= T
MAX
1
1
SCLK
MIN
4 LEADING ZEROS
4 LEADING ZEROS
0
0
= 18 MHz, f
to T
2
2
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
MAX
0
0
, unless otherwise noted.
3
3
Figure 2. AD7450A Serial Interface Timing Diagram
S
Figure 3. AD7440 Serial Interface Timing Diagram
t
t
4
4
= 1 MSPS, V
0
0
Description
t
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
4
4
SCLK
DB11
DB9
t
t
= 1/f
5
5
Rev. C | Page 7 of 28
5
5
REF
SCLK
t
t
DB10
7
7
DB8
t
t
CONVERT
CONVERT
= 2.0 V; V
DD
13
13
B
B
= 4.75 V to 5.25 V, f
DB2
DB0
8
, quoted in the Timing Specifications is the true bus relinquish
14
14
t
t
2 TRAILING ZEROS THREE-STATE
6
6
DB1
0
15
15
DB0
t
t
8
8
0
DD
DD
SCLK
= 5 V or 0.4 V or 2.0 V for V
) and timed from a voltage level of
16
16
THREE-STATE
= 18 MHz, f
t
t
QUIET
QUIET
AD7440/AD7450A
t
t
1
1
S
= 1 MSPS,
DD
= 3 V.