CS5364-CQZR Cirrus Logic Inc, CS5364-CQZR Datasheet - Page 22

• Manufacturer Part Number: CS5364-CQZR
• Description: IC ADC 4CH 114DB 216KHZ 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5364-CQZR

• Package / Case: 48-LQFP
• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 580mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPs
• Resolution: 24 bit
• Number Of Adc Inputs: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB5364 - EVALUATION BOARD FOR CS5364
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22
4.5
4.5.1 I²S and LJ Format
SCLK
LRCK
SDOUT
LRCK
SCLK
SDOUT
Serial Audio Interface (SAI) Format
The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM,
SDOUT2, SDOUT3/TDM and SDOUT4). The CS5364 output is serial data in I²S, Left-Justified (LJ), or Time
Division Multiplexed (TDM) digital audio interface formats. These formats are available to the user in both
Stand-Alone Mode and Control Port Mode.
The I²S and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are
transmitted, odd channels first, then even. The MSB is always clocked out first.
In Slave Mode, the number of SCLK cycles per channel is fixed as described under
- I²S/LJ Timing” on page
master controller, the CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per
channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK
cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Ap-
plication Note AN282.
MSB
MSB
receiver latches data on rising edges of SCLK
receiver latches data on rising edges of SCLK
Odd Channels 1,3, ...
Odd Channels 1,3, ...
15. In Slave Mode, if more than 32 SCLK cycles per channel are received from a
...
...
LSB
LSB
Figure 10. I²S Format
Figure 11. LJ Format
MSB
MSB
Even Channels 2,4, ...
Even Channels 2,4, ...
...
...
LSB
LSB
“Serial Audio Interface
CS5364
DS625F4
MSB
MSB