CS5364-CQZR Cirrus Logic Inc, CS5364-CQZR Datasheet - Page 32
![IC ADC 4CH 114DB 216KHZ 48-LQFP](/photos/16/0/160036/qfp48_sml.jpg)
CS5364-CQZR
Manufacturer Part Number
CS5364-CQZR
Description
IC ADC 4CH 114DB 216KHZ 48-LQFP
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5364-CQZ.pdf
(42 pages)
Specifications of CS5364-CQZR
Package / Case
48-LQFP
Number Of Bits
24
Sampling Rate (per Second)
216k
Data Interface
Serial
Number Of Converters
1
Power Dissipation (max)
580mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPs
Resolution
24 bit
Number Of Adc Inputs
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CDB5364 - EVALUATION BOARD FOR CS5364
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS5364-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
32
5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All
registers above 0Ah are RESERVED.
5.1
5.2
5.3
Adr
00
01
02
03
04
05
06
07
08
09
0A
R/W
R/W
R/W
RESERVED
RESERVED
RESERVED
R
Name
Register Quick Reference
OVFM
00h (REVI) Chip ID Code & Revision Register
Default: See description
The Chip ID Code & Revision Register is used to store the ID and revision of the chip.
Bits[7:4] contain the chip ID, where the CS5364 is represented with a value of 0x4.
Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented
as 0x1, etc.
01h (GCTL) Global Mode Control Register
Default: 0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data
format and the Master clock dividers for all channels. It also contains a Control Port enable bit.
Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone
Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding reg-
ister values become functional.
Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit in-
vokes 256X mode (divide XTI by 1.0 - pass through).
PDNE
MUTE
SDEN
GCTL
OVFL
REVI
HPF
CP-EN
RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED
7
7
CP-EN
7
-
-
-
RESERVED
CLKMODE
CLKMODE
6
6
CHIP-ID[3:0]
6
-
-
-
CHIP-ID[3:0]
RESERVED
PDN-BG
5
5
MDIV[1:0]
5
-
-
-
MDIV[1:0]
PDN-OSC RESERVED RESERVED
4
4
4
-
-
-
RESERVED RESERVED
OVFM4
MUTE4
OVFL4
3
3
HPF4
3
-
-
-
DIF[1:0]
DIF[1:0]
OVFM3
MUTE3
OVFL3
2
REVISION[3:0]
2
HPF3
REVISION[3:0]
2
-
-
-
OVFM2
MUTE2
PDN43
SDEN2
OVFL2
HPF2
1
1
1
-
-
-
MODE[1:0]
MODE[1:0]
CS5364
DS625F4
OVFM1
MUTE1
SDEN1
OVFL1
PDN21
HPF1
0
0
0
-
-
-