AD7715ANZ-3 Analog Devices Inc, AD7715ANZ-3 Datasheet - Page 19

• Manufacturer Part Number: AD7715ANZ-3
• Description: IC ADC 16BIT SIGMA-DELTA 16DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7715ANZ-3

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 9.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Resolution (bits): 16bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 3V To 5.25V
• Supply Current: 600µA
• No. Of: RoHS Compliant
• Sampling Rate: 19.2kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7715-3EBZ - BOARD EVALUATION FOR AD7715
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. C
and gain that can be accommodated by the part is the require-
ment that the positive full-scale calibration limit is 1.05
V
nominal range. The in-built headroom in the AD7715’s analog
modulator ensures that the part will still operate correctly with a
positive full-scale voltage which is 5% beyond the nominal.
The range of input span in both the unipolar and bipolar modes
has a minimum value of 0.8 V
value of 2.1 V
difference between the bottom of the AD7715’s input range and
the top of its input range) must take into account the limitation
on the positive full-scale voltage. The amount of offset that can
be accommodated depends on whether the unipolar or bipolar
mode is being used. Once again, the offset must take into ac-
count the limitation on the positive full-scale voltage. In unipo-
lar mode, there is considerable flexibility in handling negative
(with respect to AIN(–)) offsets. In both unipolar and bipolar
modes, the range of positive offsets which can be handled by the
part depends on the selected span. Therefore, in determining
the limits for system zero-scale and full-scale calibrations, the
user has to ensure that the offset range plus the span range does
exceed 1.05 V
a few examples.
If the part is used in unipolar mode with a required span of
0.8 V
bration can handle is from –1.05 V
GAIN. If the part is used in unipolar mode with a required span of
V
handle is from –1.05 V
larly, if the part is used in unipolar mode and required to re-
move an offset of 0.2 V
the system calibration can handle is 0.85 V
If the part is used in bipolar mode with a required span of
bration can handle is from –0.65 V
GAIN. If the part is used in bipolar mode with a required span
of V
tion can handle is from –0.05 V
GAIN. Similarly, if the part is used in bipolar mode and required
to remove an offset of 0.2 V
which the system calibration can handle is 0.85 V
Power-Up and Calibration
On power-up, the AD7715 performs an internal reset that sets
the contents of the internal registers to a known state. There
are default values loaded to all registers after a power-on or
reset. The default values contain nominal calibration coefficients
for the calibration registers. However, to ensure correct calibra-
tion for the device a calibration routine should be performed
after power-up.
The power dissipation and temperature drift of the AD7715 are
low, and no warm-up time is required before the initial calibra-
tion is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated. Similarly, if the clock source for the part is generated
from a crystal or resonator across the MCLK pins, the start-up
time for the oscillator circuit should elapse before a calibration
is initiated on the part (see below).
REF
REF
0.4 V
/GAIN, then the offset range which the system calibration can
/GAIN. This allows the input range to go 5% above the
REF
REF
REF
/GAIN, then the offset range which the system calibra-
/GAIN, then the offset range which the system cali-
/GAIN, then the offset range which the system cali-
REF
REF
/GAIN. However, the span (which is the
/GAIN. This is best illustrated by looking at
REF
REF
/GAIN to +0.05 V
/GAIN, then the span range which
REF
REF
/GAIN, then the span range
/GAIN and a maximum
REF
REF
REF
/GAIN to +0.65 V
/GAIN to +0.05 V
/GAIN to +0.25 V
REF
REF
/GAIN.
/GAIN. Simi-
REF
/GAIN.
REF
REF
REF
/
/
/
–19–
USING THE AD7715
Clocking and Oscillator Circuit
The AD7715 requires a master clock input, which may be an
external CMOS compatible clock signal applied to the MCLK IN
pin with the MCLK OUT pin left unconnected. Alternatively, a
crystal or ceramic resonator of the correct frequency can be
connected between MCLK IN and MCLK OUT in which case
the clock circuit will function as an oscillator, providing the
clock source for the part. The input sampling frequency, the
modulator sampling frequency, the –3 dB frequency, output
update rate and calibration time are all directly related to the
master clock frequency, f
frequency by a factor of 2 will halve the above frequencies and
update rate and double the calibration time. The current drawn
from the DV
Reducing f
but will not affect the current drawn from the AV
supply.
Using the part with a crystal or ceramic resonator between the
MCLK IN and MCLK OUT pins generally causes more cur-
rent to be drawn from DV
a driven clock signal at the MCLK IN pin. This is because the
on-chip oscillator circuit is active in the case of the crystal or
ceramic resonator. Therefore, the lowest possible current on
the AD7715 is achieved with an externally applied clock at the
MCLK IN pin with MCLK OUT unconnected and unloaded.
The amount of additional current taken by the oscillator de-
pends on a number of factors—first, the larger the value of
capacitor placed on the MCLK IN and MCLK OUT pins, then
the larger the DV
should be taken not to exceed the capacitor values recommended
by the crystal and ceramic resonator manufacturers to avoid
consuming unnecessary DV
mended by crystal or ceramic resonator manufacturers are in the
range of 30 pF to 50 pF, and if the capacitor values on MCLK
IN and MCLK OUT are kept in this range, they will not result
in any excessive DV
the DV
crystal which appears between the MCLK IN and MCLK OUT
pins of the AD7715. As a general rule, the lower the ESR value
then the lower the current taken by the oscillator circuit.
When operating with a clock frequency of 2.4576 MHz, there is
50 A difference in the DV
applied clock and a crystal resonator when operating with a
DV
the typical DV
resonator supplied clock versus an externally applied clock. The
ESR values for crystals and resonators at this frequency tend to
be low and as a result there tends to be little difference between
different crystal and resonator types.
When operating with a clock frequency of 1 MHz, the ESR value
for different crystal types varies significantly. As a result, the DV
current drain varies across crystal types. When using a crystal
with an ESR of 700
increase in the typical DV
clock is 50 A with DV
+5 V. When using a crystal with an ESR of 3 k , the increase in
the typical DV
100 A with DV
DD
of +3 V. With DV
DD
current is the effective series resistance (ESR) of the
CLK IN
DD
DD
DD
power supply is also directly related to f
DD
by a factor of 2 will halve the DV
DD
current increases by 200 A for a crystal/
current over an externally applied clock is
= +3 V and 400 A with DV
DD
current consumption on the AD7715. Care
or when using a ceramic resonator, the
current. Another factor that influences
DD
DD
CLK IN
DD
DD
DD
= +3 V and 175 A with DV
DD
= +5 V and f
current over an externally-applied
than when the part is clocked from
current between an externally
. Reducing the master clock
current. Typical values recom-
CLK IN
= 2.4576 MHz,
AD7715
DD
DD
DD
= +5 V.
power
current
CLK IN
DD
=
DD
.